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Any optimization tips for this...
I have never looked at the pdp8 before so I had a look at wiki page.   How fast is a OPR instruction, alway as 1 instruction or 1 for each bit that is 1  or it...
Friday, 26 April 2019 - 16:39
Any optimization tips for this...
When I (for fun) was making a AVR emulator running on a AVR, (so code could be in EEPROM or RAM etc.). I did it by reading the two bytes for the instruction (High byte into ZL and...
Friday, 26 April 2019 - 13:10
Getting started ATtiny 1 & 0 series / Application Notes
I had a quick look at the code and have to ask : Don't microchip have any internal guidelines about C style ?  This make me sad to see next to each other: void...
Monday, 22 April 2019 - 09:55
from microprocessor to AVR to SRAM
Instead of dualport RAM, you could look into a true share of the RAM.   I assume that the "real" RAM is fast (like 55ns), so if you do a sync with the AVR and the Z80 they...
Thursday, 18 April 2019 - 12:13
from microprocessor to AVR to SRAM
Ok now I see understand the question, and my question is why? :)   For what you want to do it's normal to use dualport RAM.   There is a big problem with the AVR as a...
Thursday, 18 April 2019 - 10:55
from microprocessor to AVR to SRAM
yes very little info.   I assume that you have done something like this :   so first which latch do you use ? which speed of the AVR, RAM ?
Thursday, 18 April 2019 - 09:39
Different working speeds at the same baud rate
For sure 115200 baud is 115200 baud, but that is only the speed it send a byte with, nothing about delay between bytes, between packets.   Full speed 115200 baud in this case...
Thursday, 18 April 2019 - 09:26
SREG C Bit on MUL (unsigned) instruction
But none of the should be a surprise.   The chip can wrap around, but some of the SW don't know that. Only for those with  8k or less, (and therefore don't have...
Wednesday, 17 April 2019 - 12:11
SREG C Bit on MUL (unsigned) instruction
I just copy'ed the text in AVR studio 7  
Tuesday, 16 April 2019 - 20:05
SREG C Bit on MUL (unsigned) instruction
The GCC compiler has a flag to mark if the top and buttom should be mapped around on chips bigger than 8K.(-mshort -calls ) 
Tuesday, 16 April 2019 - 18:43
Why no 14 pin AVRs with PLL?
Ask microchip. If you order 10 mill+ 20 pin chips in a 14 pin house perhaps they will do it. :)   I quick answer no big customers have asked for it.   ...
Sunday, 14 April 2019 - 09:02
Manual manipulation of Interrupt Vector Table on AVR platform
It should only be : push zh push zl ld zh ld zl ijmp and at the routine pop zl pop zh 'normal ISR code   If you reserve two (low)registers the push and pop can just be two...
Thursday, 11 April 2019 - 05:43