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The reference frequency of the DPLL96M Oscillator in SAMDA1 targets
Hello all ,   I am using the DPLL96M source in my application. In the user manual it says that the DPLL can use only external clock sources as a reference so i tested the...
Sunday, 5 April 2020 - 15:18
Digital frequency locked loop (DFLL48M) SAMDA1 Target operation Problem.
Hello All,   Does anyone know if the operation of the DFLL48M frequency source in SAMD targets depends on the used evaluation board or MCU ? !, I am facing a very...
Sunday, 5 April 2020 - 14:49
SAMDA1 PLL configuration Parameters (LDR) for max frequency
Hello All,   For PLL in register DPLLCTRLB; the LDR variable is 11 bits so its maximum value is 2048 ,which only if used with a clock source 32KHZ can generate a PLL...
Wednesday, 22 January 2020 - 12:31
96MHz PLL configuration max frequency in SAMDA1 target
Hello all,   I am facing an exception hard fault interrupt when trying to configure 96MHZ clock from the DPLL source, its reference frequency is a 16 MHz crystal. When i...
Monday, 20 January 2020 - 13:38
NVMCTRL Non volatile memory controller in SAMDA1
Hello all, When do we need to set the read wait state bit in the NVMCTRL register. In clock configuration; how does RWS bit affects the configuration of enabling any...
Monday, 13 January 2020 - 17:45
XOSC as a frequency source for FDPLL96M
Hello all,  Have anyone tried to use the XOSC external oscillator as a frequency source for the FDPLL96M?. In the data sheet in DPLL Control B register has a bit which...
Wednesday, 8 January 2020 - 09:36
XOSC clock source in SAMDA1
Hello all, I am facing a problem figuring out the configurations and the output of the XOSC oscillator. I have configured it using the following code, but i do not understand how...
Wednesday, 1 January 2020 - 14:57
Crystal oscillators for SAMDA1
Hello all,  I am concerned to know the range of the allowable crystal oscillators that can be used with Target SAMDA1. In the user manual it always mention the 32KHZ...
Monday, 30 December 2019 - 12:13
Jitter effect in PLL and DFLL output in SAMD targets
Hello all, I am experiencing the jitter effect in the generated signal from PLL and DFLL sources in SAMDA1 target, how can i generally decrease the jitter effect, and can i leave...
Monday, 23 December 2019 - 11:48
SAMDA PLL frequency stabilization
Hello all,  I am testing the generation of the PLL and i faced some issues, How can i know that the PLL has stabilized, i donot see any bit in the PLL registers that checks...
Thursday, 19 December 2019 - 13:22
XOSC clock source for SAMD targets
Hello all,  Iam trying to configure the XOSC clock source, but the output clock from it seems to not increase than 32KHZ  so what is the use of the GAIN bit in this...
Tuesday, 17 December 2019 - 12:11
OSC8M internal clock source in SAMD21
Hello everyone,  I am trying to use the clock source OSC8M and i configured it , but the output clock is not as i configure it  here is the configuration , theoretically...
Sunday, 15 December 2019 - 09:09

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