|Discussion Title||Created date|
SAML21 DPLL doesn't lock when using OSCM16M at 4MHz, locks when OSCM16M at 12MHz
Hello, I am working on ATSAML21J18B - SAML21Xplained board. I am trying to configure DPLL at 48MHz using two unidentical but similar configurations. One of...
|Tuesday, 18 June 2019 - 19:19|
SAML21 Configuring DPLL to 16MHz (no ASF)
How to configure FDPLL to output 16MHz from 12MHz OSCM source? Changing divider values not helping. Heres my code, I am configuring OSC16 at 4MHz and dividing it by 2 in GCLK...
|Monday, 17 June 2019 - 17:35|