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Serial Programming, help reading EEPROM
I found some assembly code in AN_0943 that shows that the adr MSB shall be inserted in the byte before the adr LSB. The same was also true for writing to EEPROM....
Thursday, 29 November 2018 - 12:46
Most ATTiny10 Internal Oscillator Much Slower Than Datasheet
But check the sample rate so you know the resolution of your measurement.  
Friday, 16 November 2018 - 07:18
Most ATTiny10 Internal Oscillator Much Slower Than Datasheet
Note: You are also limited by the logic analyzer sampling rate. This gives the final resolution of your measurement. Enable only one logic channel on and sample it using the...
Thursday, 15 November 2018 - 15:58
Single step debug an ATtiny44A? Is it possible?
I think I found out how to do. I must get a Atmel-ICE debugger (for example). It can communicate with the ATtiny using DebugWire (serial communication through the RESET-pin). That...
Thursday, 25 October 2018 - 21:09
Is it still possible to enter serial programming mode if RSTDISBL fuse bit is programmed?
Ok. But what about the statement in the datasheet?   If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4 ms to ensure programming mode can be...
Monday, 1 October 2018 - 09:08
Serial programming ATtiny24A fails sometimes. Too high oscillator frequency?
Looks like it is working now every time (programmed the CKDIV8). I have tested at least 200 times.  
Thursday, 17 May 2018 - 11:21
Serial programming ATtiny24A fails sometimes. Too high oscillator frequency?
Yes I mean Serial Programming through SPI.   The SPI SCK is run at 125 kbit/s, so that is OK.   What I mean is that the datasheet say that if Vcc = 1.8 -...
Thursday, 17 May 2018 - 10:22
AVR Errata - Unpublished, and other "Gotchas"
AVR910: In-System Programming APPLICATION NOTE   The document states that Programming Enable command ($AC 53 xx yy) gets reply ($zz AC 53 xx).   That is not correct...
Tuesday, 27 March 2018 - 15:13
Attiny24A. Startup delay. How long is one CK?
ka7ehk wrote: MASIP is correct in the conclusion:   So if I use en 8 MHz external oscillator that is divided internally by 8 then fCK is 1MHz? And if I use en 8 MHz external...
Monday, 26 March 2018 - 16:40
Attiny24A. Startup delay. How long is one CK?
ka7ehk wrote: "CK" represents the period of the system clock. The block diagram is slightly misleading (not a new thing). You are correct that it shows no external inputs but note...
Monday, 26 March 2018 - 15:32
Attiny24A. Startup delay. How long is one CK?
frog_jr wrote: CK would be the period of what ever your chosen clock source might be.   Where can I read this statement? In the second picture in my posting the clock...
Monday, 26 March 2018 - 15:18
Attiny24A. Startup delay. How long is one CK?
Could the "clock generator" be similar to the "watchdog oscillator". The watchdog oscillator looks like it could be an RC-oscillator of some sort.
Monday, 26 March 2018 - 15:14

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