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[resolved, embarrassed] unsure why RESRDY is not clearing [edit] initializing ADC0 only but using them both is a recipe for random outcomes. OK, not random, but unexpected. 96MHz DPLL / 16 for a 6MHz ADC clock. ... |
Wednesday, 10 April 2019 - 17:45 |
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fastest simultaneous ADC in SAM series? I want to replace a TMS320 that is running synchronous and simultaneous I/Q ADC on a 160ns (6.25MSa/s) period - and I'd like to attain and use the 80ns (12.5MSa/a) of the the... |
Wednesday, 13 February 2019 - 12:14 |
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reconfigure START for a different processor? I have a sample program from tech support to use TCM for 'execution from sram'. it is for the E54 xplained, but I want to configure it for my D51G19A board, which is custom... |
Tuesday, 15 January 2019 - 20:59 |
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source code for TB3186 (loading code to TCM) http://ww1.microchip.com/downloa... explains it, but the code sample is an image in the document. Does anyone have an example - ideally for ATSAMD5x - as an editable file?... |
Wednesday, 24 October 2018 - 13:29 |
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Atmel Studio, START - reconfigure MCU from SAMD51 to SAME54??? I swear the easier developers try to make a tool to use, the harder it is to do some things... Is this even possible? |
Monday, 15 October 2018 - 19:44 |
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Feeling inept with SAME54 eval and trivial UART... 32KHz ext osc --> 120 MHz MCU and 96MHz clock for UART. Intention was to test fastest reasonable on-board serial lines, hence the name. 96MHz clock divided as GCLK2... |
Friday, 12 October 2018 - 13:21 |
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has anyone here tried C# on a SAMD5x? For the life of me, I wouldn't do it, but I have been asked. I see general references to dot-net for core M4, so perhaps it is possible. I'd want to do the working... |
Saturday, 8 September 2018 - 16:40 |
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ATSAMD51 - load code segments to sram at boot? I will have some tight loops that really need to be sped up. Similar code in a TMS320C2809 had to be loaded to sram for execution to avoid the wait states. Is there a... |
Tuesday, 28 August 2018 - 11:56 |
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(solved while posting) ATSAMD51 counter, 32bit, retrieving the count?? Pretty simply, the CPU clock (GCLK0) really is running 120MHz. The first function is doing what it claims - OK, taking it on faith that it counts, but it is clocked from a valid... |
Saturday, 4 August 2018 - 20:48 |
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ATSAMD51 ADC Errata clarification 1.1.2 ADC The ADC TUE/INL/DNL performance is not guaranteed in the following scenarios: • Sampling frequency is above 500 ksps • ADC VREF is different from VDDANA Workaround None... |
Monday, 23 July 2018 - 19:10 |
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ATSAMD51 NVM questions I am sure I looked right at it, but for the life of me... I need to roll my own bootloader (integrated into an app that we already have for loading hex files to dsPIC33 and... |
Wednesday, 18 July 2018 - 17:54 |
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question about xxx.INTENSET.bit.yyy I have code that uses various interrupts that are enabled and disabled on the fly. At some point this week it seems like, for example, SERCOM3->USART.INTENCLR.bit.DRE = 1... |
Monday, 7 May 2018 - 02:21 |