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C21 DIVAS Block and GCC
Correct you need a M3 for hardware divide inside the core.   However:   Its not that bad a situation, the DIVAS is quite nice, and also quick. If i was using a C21, and...
Tuesday, 6 October 2015 - 14:55
C21 DIVAS Block and GCC
GCC wont make use of DIVAS automatically, because its not part of the core, it is a peripheral on the bus.  So there is no change to the core, its just a Coretex M0+.  ...
Tuesday, 6 October 2015 - 13:28
Poor Code generation for M0 Arm Cores
Ok,   Now i am convinced that the GCC optimiser for Cortex-M0 is not only very bad, it is buggy.  And if you don’t want to read all this, skip to the end for a potential...
Tuesday, 6 October 2015 - 11:23
Poor Code generation for M0 Arm Cores
donotdespisethesnake wrote: Upvoted :) Appreciate it, thanks.   Quote: Hopefully it gets a better response than "change your code"! If ARM want M0 to replace 8 bitters, then...
Sunday, 4 October 2015 - 15:36
Poor Code generation for M0 Arm Cores
Ok I filed the bug report.  Really the M0 code generation is terrible and it seems completely unnecessary.  My test case does not generate any M3 specific instruction...
Sunday, 4 October 2015 - 13:32
Poor Code generation for M0 Arm Cores
So i have reduced my test code to explore the issue further.  I think its a different problem to the bug report I added to, although it is Similar.   It is, as far as i...
Sunday, 4 October 2015 - 04:42
SAMD21 port(s)
If your port pins are 8 bit contiguous and 8 bit aligned you can do it with a single 8 bit write of your new value to the register. Writing only 8 bits will not effect the other...
Saturday, 3 October 2015 - 02:23
SAMD21 port(s)
I concur with everyone that ASF is a fat bloated hog.  I am writing a low level driver library for the L21, and the L21 and D21 are similar enough it will probably work on a...
Friday, 2 October 2015 - 01:19

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