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Headache due to Atmel answers
Atmel final response: Quote:Yes, in the 24-bit bus internal SRAM gets high priority followed by external memory (through chip select). The actual external memory is (16MB-...
Monday, 12 August 2013 - 19:10
Headache due to Atmel answers
ezharkov wrote: 0x0 is perfectly valid base address too. Except that in this case you "lose" part of SDRAM that overlaps with the internal memory. I agree. david.prentice wrote:Do...
Thursday, 8 August 2013 - 16:03
Headache due to Atmel answers
david.prentice wrote:You should never worry about the chip's internal addressing. Just compile your code and let the Compiler / Linker sort it out. This case is not an internal...
Thursday, 8 August 2013 - 14:58
Headache due to Atmel answers
david.prentice wrote:Why not just test it for yourself? Do you have 16M x 8 of SDRAM ? The Xplained boards have got 8MB onboard SDRAM by using a 16M x 4 bit chip. I don't know...
Thursday, 8 August 2013 - 13:53
My XMEGA based electronic organ
DocJC wrote:Very Nice! Thanks,JC. Torby wrote:How appropriate! Toccata and Fugue in D Minor This is one of my favorite musics and I have played it completely some years ago....
Saturday, 3 August 2013 - 18:53
Tone Library for xmega
Not for using DAC, but as a pulse generator for melody generation, my project may help:
Monday, 8 July 2013 - 16:32
Direct replacement of 128a1 with 128a1u?
There are some differences between A and AU series. For example, DACx.TIMCTRL is one of DAC registers in A series. But this register is not present at all in AU series.
Monday, 8 July 2013 - 03:50
Moving from AVR to XMEGA
MKControls wrote: Appreciate any help!!! 1- Stack pointer initialization is automatically done by cpu in XMEGA. 2- There is a main difference when writing 16bit registers. For AVR...
Sunday, 30 June 2013 - 07:28
PWM Hi-Res
TCD0.PER = 255; From Manual when using Hi-Res: Quote:The two lsb of the timer/counter period register must be set to zero to ensure correct operation.
Sunday, 23 June 2013 - 10:55
AC event to GPIO
AC event lasts only for one clock cycle and this can not be detected by an LED. Quote:An event normally lasts for one peripheral clock cycle, but some event sources, such as a low...
Saturday, 9 February 2013 - 05:22
Delay after ADC conversion complete.
Setting CH0IF flag by cpu is AFTER updating CH0RES. So there is no need for such a delay before reading the result.
Saturday, 9 February 2013 - 05:10
XMEGA, DMA and timers – how to keep in sync.
TFrancuz wrote:CNT cannot be equal to PER, when it is equal it will be cleared and overflow event will be signaled. This is an incorrect assumption: Quote:The counter reaches TOP...
Friday, 8 February 2013 - 16:36