Post Created date
SAMD21 double interrupt after deep sleep
So with some help from Microchip support they enlightened me that I need to clear the event flag:  EVSYS->INTFLAG.reg = EVSYS_INTFLAG_EVD0;Before I turn it back on:...
Monday, 20 May 2019 - 22:48
samd21 PLL vs DFLL
Thanks for the information, we did switch to DPLL as well, but I had not noticed any real differences in our application where the device will sleep for 20-30 seconds at a time...
Wednesday, 16 May 2018 - 20:27
SAMD21 TC sync fixes short sleep?
So the way FreeRTOS implemented tickless last year (hopefully they have updated since then) was to use a 32 bit Timer/Counter (like TC4/5) running of your 48 MHz clock to control...
Wednesday, 16 May 2018 - 20:21
SAMD21 Timer/Counter Callback jitter when reading multiple TC values
This is one of those cases where you can't completely believe the datasheet. If you look in gclk.h for samd21 you will see the pairings.   #define...
Wednesday, 16 May 2018 - 17:45
SAMD21 TC sync fixes short sleep?
Greetings,  since I posted this we have switched from FreeRTOS to a TNEO derivative that allows for a better tickless implementation.  What we have discovered is that...
Wednesday, 16 May 2018 - 17:33
Set pulldown on sama5d36 input pin in dts file
Figured it out, just needed to get the SPI dts settings correct, turn off all peripherals, realize that some pins are pulled up in hardware, including some LED settings and I can...
Wednesday, 14 March 2018 - 14:37
Set pulldown on sama5d36 input pin in dts file
Not getting much of a response so I am going to try posting this question in the Microchip forum:   Look there if I...
Thursday, 22 February 2018 - 22:46
Set pulldown on sama5d36 input pin in dts file
Just wanted to add that I do see PULL_DOWN in /sys/kernel/debug/pinctrl/ahb:apb:pinctrl@fffff200/pinconf-pins:   pin 30 (pioA30): PULL_DOWN|DRIVE_STRENGTH_MED pin 31 (pioA31...
Wednesday, 14 February 2018 - 18:41
DFLL gives 46.9 MHz instead of 47.9 MHz
I just threw a water bottle at the wall!!! That is so obvious now, I wasn't waiting for it to lock like I thought.  Thanks for the insight.
Tuesday, 23 January 2018 - 23:15
DFLL gives 46.9 MHz instead of 47.9 MHz
Yes, measured it out one of the pins in a similar fashion to GCLK0.  I was thinking there might be some strange issue with our crystal, thus why I tried it on the xplained...
Tuesday, 23 January 2018 - 16:18
GCLK->GENCTRL and structure initialization
Thanks Lars,  That does work and the assembly comes out optimized down to just the address, very similar to the more traditional method.  Any insight on why gcc doesn't...
Friday, 5 January 2018 - 23:38
standby wake from UART causes inability to program board
Turns out that how you tweak the DFLL can be a big part of the issue.  Here is a quote from Microchip support:   another issue is the STABLE bit of the DFLLCTRL. When...
Friday, 27 October 2017 - 20:55