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AT32UC3 Address_1 Signal problem
I'd bet the solution to your problem (if there is one) lies in chapter 16 - HSB Bus Matrix (HMATRIXB) of the UC3C data sheet. Setting the PDCA as fixed default master might be...
Sunday, 8 May 2011 - 22:41
Inline assembly with double-word arguments
LD.D – Load Doubleword ST.D – Store Doubleword Remember, this is a 32 bit risc architecture.
Thursday, 5 May 2011 - 22:43
LD.W instruction syntax
Try: LD.W R3, R2[R5:b] I'd be really surprised if the "<<2" should be included as the shift is implicit in the instruction.
Monday, 2 May 2011 - 22:26
[SOLVED] Basics: Exact moment of interrupt
From the AVR32 Architecture Document: "Since the INTx exception is unrelated to the instruction stream, the instructions in the pipeline are allowed to complete. After finishing...
Sunday, 10 April 2011 - 17:46
[SOLVED] GPIO / local bus problems on UC3C
Binarus wrote:Therefore, we were expecting that at least the toolchain is reliable. But this is not the case; instead, describing all linker, compiler and assembler bugs which I...
Monday, 21 March 2011 - 10:44
problem with custom bootloader
Did you flashc_set_wait_state (1); ? This is necessary for clock speeds above 33 MHz.
Friday, 28 January 2011 - 23:43
Bus Error Data Fetch and serial
What is the frequency of your clock?
Friday, 21 January 2011 - 00:57
Suggest me a chip
Sunday, 2 January 2011 - 00:55
High precision encoders
This will accomplish the desired resolution and accuracy (and then some!) but it isn't cheap.
Friday, 17 December 2010 - 23:58
How to do _PC PCI to AVR32 (AT32UC3A0...) ?
PCI multiplexes the address and data bus so you'll need some not-so-trivial hardware between PCI and EBI.
Tuesday, 19 October 2010 - 10:42
registers used by c functions
GCC puts the first parameter in R12, 2nd in R11, 3rd in r10, and 4th in r9. 5th and higher parameters are pushed on the stack. The return address is in LR (R14). GCC does not...
Wednesday, 15 September 2010 - 23:28
Software differences between AVR32UC3A and B?
Also, AVR32 Studio sets __AVR32_UC__ to the arch revision level (currently 1, 2, or 3) so you can set up conditional assembly to take advantage of the later rev instructions while...
Wednesday, 8 September 2010 - 23:17