XRAM device selection

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G'day all,

I'm doing a project involving the ATMEGA128 and external ram and it is about this last bit that I post. The XRAM interface on the 128 has /WR and /RD control lines whereas all SRAM I have come across had /OE and /WE control lines. Conversions between the two are pretty simple with some external logic, but space is critical and external logic would really not be too good. I have seen some circuits where the /RD and /WR pins are directly connected to /OE and /WE but I just can't see how this would work.

Does anyone have information on RAM with the /RD /WR control, or is there some way around this?

Cheers,
S.

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The short answer is
Connect /OE to /RD and /WE to /WR
The longer answer is
/OE = Output Enable. The chip will output on the data bus, the addressed data when /OE is active. The AVR will make /RD active when it wants to read the data bus.
/WE = Write Enable. The chip will latch whatever is on the data bus, and stick it wherever the address points to. The AVR will make /WR active when valid data is on the bus.

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Just use the direct connection /RD to /OE and /WR to /WE The functionality of the pins is 1:1, and the drive capability is OK.

If the RAM is the only external device, you can keep the RAM /CE low all the time at the expense of increased power consumption. If that is not acceptible you have to derive the /CE signal from the ALE, /RD and /WR signals. That cost some logic.

Check the Atmel datasheet regarding the address latch, and observe that the memory read/write timing with your RAM is OK, else add wait cycles by setting the MCUCR accordingly.

If you use WinAVR and put variables in the external RAM, also remember to set the MCUCR register as described under this post to avoid the hen/egg problem using external variables at program start:

https://www.avrfreaks.net/index.p...

Erik