xmega32E5 XCL 1shot PWM problem

Go To Last Post
3 posts / 0 new
Author
Message
#1
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I would like to output two 1shot pulses using xmega32E5's XCL.

When only BTC0 is used, one pulse output is obtained.
However, when BTC0 and BTC1 are used, neither pulse output is obtained.

What am I doing wrong?

 

#include <avr/io.h>

int main(void){
    // init PORT0
    PORTCFG.MPCMASK = 0b11111111;
    PORTA.PIN0CTRL = PORT_ISC_INPUT_DISABLE_gc;

    PORTCFG.MPCMASK = 0b11011111;
    PORTC.PIN0CTRL = PORT_ISC_INPUT_DISABLE_gc;
    PORTC.PIN5CTRL = PORT_ISC_RISING_gc;    // for XCK
    PORTC.DIR = 0b10110001;

    PORTCFG.MPCMASK = 0b11111111;
    PORTD.PIN0CTRL = PORT_ISC_INPUT_DISABLE_gc;
    PORTD.DIR = 0b00001100;

    PORTR.PIN0CTRL = PORT_OPC_PULLUP_gc;
    PORTR.PIN1CTRL = PORT_OPC_PULLUP_gc;
    
    // init SPIC
    SPIC.CTRLB = SPI_BUFMODE_BUFMODE2_gc | SPI_SSD_bm;
    SPIC.CTRL = SPI_ENABLE_bm | SPI_MASTER_bm | SPI_MODE_0_gc | SPI_PRESCALER_DIV16_gc;

    // init EVSYS
    EVSYS.CH0MUX = EVSYS_CHMUX_PORTC_PIN5_gc;

    // init XCL BTC
    XCL.PERCAPTL = 10;  // BTC0 period
    XCL.PERCAPTH = 10;  // BTC1 period
    XCL.CMPL = 3;       // BTC0 shot width
    XCL.CMPH = 3;       // BTC1 shot width
    XCL.CTRLG = XCL_EVACTEN_bm | XCL_EVACT1_RESTART_gc | XCL_EVACT0_RESTART_gc | XCL_EVSRC_EVCH0_gc;
    XCL.CTRLF = XCL_MODE_1SHOT_gc | XCL_CCEN1_bm | XCL_CCEN0_bm;

    XCL.CTRLE = XCL_TCSEL_BTC0_gc | XCL_CLKSEL_DIV1_gc;     // OK(BTC0 only)
//  XCL.CTRLE = XCL_TCSEL_BTC01_gc | XCL_CLKSEL_DIV1_gc;    // NG(BTC0 & BTC1)

    // main loop
    while (1){
       if (SPIC.STATUS & SPI_DREIF_bm){
            SPIC.DATA = 0x55;
        }
    }
}

 

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Don't you need to set the mode in XCL.CTRLE before doing the register setup that depends on this.

/Lars

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I tried narrowing down the problem by further reducing the code.

 

The operation of PERCAPT and CMP is strange.

It seems that the two registers are linked.

 

In the BTC0 mode, since CMPL and CMPH are exchanged, it can be used without problems by chance.

(Without manipulating PERCAPTH and CMPH)

 

Is not this an unknown errata?

 

#include <avr/io.h>
#include <avr/cpufunc.h>

volatile uint8_t copy_perl, copy_perh, copy_cmpl, copy_cmph;

int main(void){

    // init XCL BTC
    XCL.CTRLF = XCL_MODE_1SHOT_gc | XCL_CCEN1_bm | XCL_CCEN0_bm;
    XCL.CTRLE = XCL_TCSEL_BTC01_gc;     // two 8bit mode(BTC0 & BTC1)
//  XCL.CTRLE = XCL_TCSEL_TC16_gc;      // 16bit mode

    // set PER
    XCL.PERCAPTL = 0x01;    // BTC0 period
    XCL.PERCAPTH = 0x02;    // BTC1 period

    // read resister1
    copy_perl = XCL.PERCAPTL;
    copy_perh = XCL.PERCAPTH;
    copy_cmpl = XCL.CMPL;
    copy_cmph = XCL.CMPH;
    _NOP();                 // break point1

    // set CMP
    XCL.CMPL = 0x03;        // BTC0 shot width
    XCL.CMPH = 0x04;        // BTC1 shot width

    // read resister2
    copy_perl = XCL.PERCAPTL;
    copy_perh = XCL.PERCAPTH;
    copy_cmpl = XCL.CMPL;
    copy_cmph = XCL.CMPH;
    _NOP();                 // break point2

    while (1);
}