I'm having issues with the 32MHz internal oscillator on a Xmega32E5. The 2MHz clock checks out fine. I also tried enabling the 8MHz oscillator and using PLL for 32MHz and that works fine. However, if I attempt to use the 32MHz oscillator, I'm seeing a ~60MHz clock at a much lower amplitude (~2.25vpp). The same code I'm using works fine on a Xmega8E5 which produces a stable (enough) 32MHz clock. Using DFLL against the internal 32KHz clock doesn't make a difference. Is the internal 32MHz oscillator just hosed or is there anything I can do to fix it? Any troubleshooting tips? Thanks!
I'm watching the clock on PC4 with the following:
PORTC_DIRSET = PIN4_bm; PORTCFG_CLKOUT |= PORTCFG_CLKOUT_PC7_gc; PORTCFG_CLKOUT |= PORTCFG_CLKEVPIN_PIN4_gc;
32MHz w/ DFLL code:
OSC.CTRL |= OSC_RC32MEN_bm | OSC_RC32KEN_bm; /* Enable the internal 32MHz & 32KHz oscillators */ while(!(OSC.STATUS & OSC_RC32KRDY_bm)); /* Wait for 32Khz oscillator to stabilize */ while(!(OSC.STATUS & OSC_RC32MRDY_bm)); /* Wait for 32MHz oscillator to stabilize */ DFLLRC32M.CTRL = DFLL_ENABLE_bm ; /* Enable DFLL - defaults to calibrate against internal 32Khz clock */ CCP = CCP_IOREG_gc; /* Disable register security for clock update */ CLK.CTRL = CLK_SCLKSEL_RC32M_gc; /* Switch to 32MHz clock */ OSC.CTRL &= ~OSC_RC2MEN_bm; /* Disable 2Mhz oscillator */
32MHz via 8MHz PLL:
OSC.PLLCTRL = OSC_PLLSRC_RC8M_gc | OSC_PLLFAC2_bm; OSC.CTRL |= OSC_PLLEN_bm | OSC_RC8MEN_bm; while(!(OSC.STATUS & OSC_PLLRDY_bm)); /* Wait for PLL to stabilize */ while(!(OSC.STATUS & OSC_RC8MRDY_bm)); /* Wait for RC8 to stabilize */ CCP = CCP_IOREG_gc; /* Disable register security for clock update */ CLK.CTRL = CLK_SCLKSEL_PLL_gc; /* Switch to PLL clock */