Just to clarify a few things in my mind with the above I carried out some tests, the good news is that it seems pretty much impossible for anyone of average intelligence to lock the chip, but one cannot ever underestimate the sheer brilliance of some people to do the impossible.
The better news is that there is no bad news at the moment.
The board is preset to use JTAG for programming and debug and I'm referring to the use of JTAG Mk3 in the following.
If anyone wants to try out PDI instead or wants/needs to use at least 3 pins of PORTB (PB3-PB6), which are usually JTAG, the simple thing to do is to disable the JTAG fuse with JTAG itself.
Studio will swear at you a couple of times for doing it but simply close the swear windows, select PDI from the dropdown menu of the programming window and you are back in control.
The same thing applies in reverse, going from PDI back to JTAG, simply enable JTAGEN with PDI, put up with a couple of insults from Studio, select JTAG and all is well.
If you also want/need to use PB7 (TDO) then you need to perform minor surgery at the back of the board, just cut the marked track near the JTAG/PDI header, making sure that you are already in PDI mode first by disabling JTAG as above, and all 4 JTAG pins are available to use. These appear on J3.
The reason for the above is that pin 5 of the header is shared by both JTAG and PDI, if JTAG is not disabled then the PDI data is shorted out by TDO. As to why it is so when there is a spare pin on the header ( pin 8 ) I don't know, but there must be a reason, maybe backward compatibility
All of the above is probably in the manual but who reads them... If anyone knows more or thinks the above is not correct please Xplain. :)