Xmega128D4 32MHz clock PLL problem?

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I'm trying to change the system clock from the external crystal @16MHz to PLL x2 using the external crystal @16MHz as the clock source.

 

The code was generated by the CV wizard, but it gets stuck at waiting for the PLL to stabilise.

 

 

I'm suspecting some optimisation issue and have tried the "normal" O1, then Os and O3, I have removed the CV optimisation pragma and replaced the asm "cli"; bit with the cli(); of GCC.

 

This is the code generated by CV:

// System Clocks initialization
unsigned char n;

    cli();
    
// External 16000.000 kHz clock source on XTAL1 initialization
OSC.XOSCCTRL=OSC_XOSCSEL_EXTCLK_gc;
// Enable the external clock source
OSC.CTRL|=OSC_XOSCEN_bm;

// System Clock prescaler A division factor: 1
// System Clock prescalers B & C division factors: B:1, C:1
// ClkPer4: 32000.000 kHz
// ClkPer2: 32000.000 kHz
// ClkPer:  32000.000 kHz
// ClkCPU:  32000.000 kHz
n=(CLK.PSCTRL & (~(CLK_PSADIV_gm | CLK_PSBCDIV1_bm | CLK_PSBCDIV0_bm))) |
    CLK_PSADIV_1_gc | CLK_PSBCDIV_1_1_gc;
CCP=CCP_IOREG_gc;
CLK.PSCTRL=n;

// PLL initialization
// PLL clock source: External Osc. or Clock
// PLL multiplication factor: 2
// PLL frequency: 32.000000 MHz
// Set the PLL clock source and multiplication factor
n=(OSC.PLLCTRL & (~(OSC_PLLSRC_gm | OSC_PLLFAC_gm))) |
    OSC_PLLSRC_XOSC_gc | 2;
CCP=CCP_IOREG_gc;
OSC.PLLCTRL=n;
// Enable the PLL
OSC.CTRL|=OSC_PLLEN_bm;

// System Clock prescaler A division factor: 1
// System Clock prescalers B & C division factors: B:1, C:1
// ClkPer4: 32000.000 kHz
// ClkPer2: 32000.000 kHz
// ClkPer:  32000.000 kHz
// ClkCPU:  32000.000 kHz
n=(CLK.PSCTRL & (~(CLK_PSADIV_gm | CLK_PSBCDIV1_bm | CLK_PSBCDIV0_bm))) |
    CLK_PSADIV_1_gc | CLK_PSBCDIV_1_1_gc;
CCP=CCP_IOREG_gc;
CLK.PSCTRL=n;

// Wait for the PLL to stabilize
while ((OSC.STATUS & OSC_PLLRDY_bm)==0);

// Select the system clock source: Phase Locked Loop
n=(CLK.CTRL & (~CLK_SCLKSEL_gm)) | CLK_SCLKSEL_PLL_gc;
CCP=CCP_IOREG_gc;
CLK.CTRL=n;

// Disable the unused oscillators: 2 MHz, 32 MHz, internal 32 kHz
OSC.CTRL&= ~(OSC_RC2MEN_bm | OSC_RC32MEN_bm | OSC_RC32KEN_bm);

// ClkPer output disabled
PORTCFG.CLKEVOUT&= ~(PORTCFG_CLKOUTSEL_gm | PORTCFG_CLKOUT_gm);

and YES the crystal IS working just in case....

This topic has a solution.

John Samperi

Ampertronics Pty. Ltd.

www.ampertronics.com.au

* Electronic Design * Custom Products * Contract Assembly

Last Edited: Mon. Apr 30, 2018 - 09:16 PM
This reply has been marked as the solution. 
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It's been a while since I've done anything with an XMEGA, but I think the code above is configuring it for an external clock, not a crystal:

 

// External 16000.000 kHz clock source on XTAL1 initialization
OSC.XOSCCTRL=OSC_XOSCSEL_EXTCLK_gc;
// Enable the external clock source
OSC.CTRL|=OSC_XOSCEN_bm;

 

 

 

Greg Muth

Portland, OR, US

Xplained/Pro/Mini Boards mostly

 

Make Xmega Great Again!

 

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I think the code above is configuring it for an external clock, not a crystal:

hmmm I must have told CV the wrong thing, of course it doesn't help not knowing what I'm doing. blush

 

Copied that line from the 16MHz version of the init and it's all good, thank you.

// External 16000.000 kHz clock source on XTAL1 initialization
// OSC.XOSCCTRL=OSC_XOSCSEL_EXTCLK_gc;

OSC.XOSCCTRL=OSC_FRQRANGE_12TO16_gc | OSC_XOSCPWR_bm | OSC_XOSCSEL_XTAL_16KCLK_gc;

// Enable the external clock source
OSC.CTRL|=OSC_XOSCEN_bm;

 

John Samperi

Ampertronics Pty. Ltd.

www.ampertronics.com.au

* Electronic Design * Custom Products * Contract Assembly