Xmega128A1 ADC

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I remember reading something about the original ADC having some "issues" but I don't know if this is affecting my readings.

Trying to read the pot on the Xplain board on portB bit 1.

Portb is all inputs with pulldown resistors except PB1 which doesn't have pull up/down.

	ldi		temp1,PORT_OPC_PULLDOWN_gc	; Turn on pull down resistors

	ldi		temp, ~ (1<<PIN1_bp)		; 0xfd No pull up/down on PB1
	STORE	PORTCFG_MPCMASK, temp
	STORE	PORTB_PIN0CTRL,temp1

I have verified that this is correct with the JTAG

After the init a do a test ADC read but it doesn't seem to work, maybe someone can spot something wrong.

	ldi		temp, ADC_RESOLUTION_12BIT_gc	; Set resolution for 12bit 
	STORE	ADCB_CTRLB, temp
	ldi		temp, ADC_REFSEL_VCC_gc			; Use internal voltage reference divider VCC/1.6. 
	STORE	ADCB_REFCTRL, temp
	ldi		temp, ADC_PRESCALER_DIV16_gc	; Divide clock by 16 (4MHz/16 = 250KHz) 
	STORE	ADCB_PRESCALER, temp 
	ldi		temp, ADC_CH_INPUTMODE_SINGLEENDED_gc	; Single ended input mode 
	STORE	ADCB_CH0_CTRL, temp
	clr		temp
	STORE	ADCB_CH0_INTCTRL, temp			; Disable interrupts 
	ldi		temp, ADC_ENABLE_bm				; Enable the ADC 
	STORE	ADCB_CTRLA, temp


	ldi		temp, ADC_CH_MUXPOS_PIN1_gc		; Select PORTB PIN1 (Pot Output) 
	STORE	ADCB_CH0_MUXCTRL, temp

	ldi		temp, ADC_CH_START_bm			; Start conversion on channel 0 
	STORE	ADCB_CH0_CTRL, temp

WAIT_ADC_init:
	SKBS	ADCB_CH0_INTFLAGS, ADC_CH0IF_bp, temp2	;Wait for conversion to finish 
	rjmp	WAIT_ADC_init

	ldi		temp, ADC_CH_CHIF_bm			; Clear flag
 	STORE	ADCB_CH0_INTFLAGS, temp

	LOADW	temp, temp1,ADCB_CH0RES

the last instruction loads up temp and temp1 with the results register.

The C code snippet I have puts a 5ms delay before reading ADCB_CH0RES for some reason, don't know it is is because of the "issues" the ADC has.

Pretty tired now, I'll have another go tomorrow. This is the last bit to test before I start with the real Xmega I'll end up using ( :wink: only a few people know what I mean) on the proper board, very happy with the rest of the code being ported to the Xmega.

John Samperi

Ampertronics Pty. Ltd.

www.ampertronics.com.au

* Electronic Design * Custom Products * Contract Assembly

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There is a (maximum) 24 ClkADC cycles start-up time after enabling ADC. Also 7 ClkADC cycles needed (accoring to A3U datasheet) for settling time after changing input mode. ADC enablinng can be done after all settings and then a sufficient delay and then starting the ADC conversion. This delay is not present in your code.
Note:Before using ADC, calibration values must be loaded.

Ozhan KD
Knowledge is POWER

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Thank you, I'll try to digest things during the day. :-)

John Samperi

Ampertronics Pty. Ltd.

www.ampertronics.com.au

* Electronic Design * Custom Products * Contract Assembly

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I ended using PA0 as external voltage reference for the ADC and subtracted 150 from the results for anything above 150 for the offset.

The little pot on the Xplain board is also a bit of a pain to use.

Added a 1ms delay in a couple of places for now, I was also thrashing ADCB_CH0_CTRL above :oops: instead of setting just a single bit.

It's good enough for my tests, can't do much more code wise until a get a proper PCB, maybe towards the end of January.

About 95% of the code runs well one the Xmega now, the other 5% needs the rest of the hardware in place. Then I can do finer adjustments. Maybe I will understand things a bit more by then.

John Samperi

Ampertronics Pty. Ltd.

www.ampertronics.com.au

* Electronic Design * Custom Products * Contract Assembly