XMEGA new informations from Atmel support

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#1
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I asked about slew rate value for XMEGA port pins. The Atmel answer contains some new information, which is not present in XMEGA manuals and datasheets.

Quote:
The effect of the slew rate limitation will be highly dependent on load.
The table below shows typical values for a disconnected pin.

---------------------------------------------------------------------------
--------------------
1.8V 2V 2.4V 2.7V 3V 3.6V
---------------------------------------------------------------------------
--------------------
No slew rate limit 18ns 11ns 8ns 7ns 7ns 6ns
Slew rate limit enabled 25ns 20ns 13.ns 10ns 9ns 7ns

Please note that these values are with respect to XMEGA A devices.


I asked again:
Quote:
I'm confused by your answer. The slew rate unit is volt/s,volt/us,etc.
Does your answer mean a time of 18ns for going from 0v to 3.6v and 6ns for going from 0v to 1.8v? If this is the case, your numbers seem to be in reverse order. Also if this is true, there is a nonlinearity in port slew rate. beceause when there is a need for 6ns of time for going from 0 to 1.8v, this would be 12ns (and not 18ns) for going from 0 to 3.6v. Otherwise the port slew rate is nonlinear with respect to Vcc.

Atmel:
Quote:
The table is correct and it takes 18ns to reach from 0 to 1.8V and it takes 6ns to reach from 0 to 3.6V. The driver strength of the pads is much better at high Vcc.

Ozhan KD
Knowledge is POWER

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Interesting info. What are you using xmega for anyway Ozhan?

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GordonFreeman wrote:
What are you using xmega for anyway Ozhan?

I use XMEGA for my current controlled stepper motor microstepping driver.

Ozhan KD
Knowledge is POWER

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I asked about ADC result registers with different address and names.
Atmel:

Quote:
The two registers in ATxmega devices (for example ADCA_CH0RESL and ADCA_CH0_RESL) are actually holding the same result from the ADC. The reason for having this is to enable easier C-code implementation.

Ozhan KD
Knowledge is POWER

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electronic.designer wrote:
I asked about ADC result registers with different address and names.
I don't understand what you were asking about?
Was it a question about the low and high result registers?

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atomicdog wrote:
I don't understand what you were asking about?
Was it a question about the low and high result registers?

There are 2 sets of ADC result registers in XMEGA. For example, ADCA_CH0RESL and ADCA_CH0RESH are low and high bytes of ADCA channel0 result registers. Also ADCA_CH0_RESL and ADCA_CH0_RESH are present, which are different in name and address. Atmel says both are holding the same values.

Ozhan KD
Knowledge is POWER

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Oh, I missed that extra underscore. I see now.

Did they say why this makes writing C code easier?

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Quote:

Did they say why this makes writing C code easier?

Is there a block of registers in one place and do they cast a struct onto it any any chance? (of course that still doesn't explain the "other" set of registers if they are out on their own somewhere else ;-))