According to XMEGA A manual,maximum clock for SPI module is clkper/2. But the following was also written in SPI section:
doc8077-Rev H- page 230:
In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of this clock signal, the minimum low and high periods must be:
Low period: longer than 2 CPU clock cycles.
High period: longer than 2 CPU clock cycles.
This means a maximum clock of clkper/4 in slave mode. I asked this issue from atmel support and the answer indicates clkper/2 is only valid for master SPI and not for slave mode:
Regarding your question about the SPI speed: You are correct that the clkper/2 rate is only applicable when running the XMEGA as a SPI master. When the XMEGA acts as the master, it is in control of the clock; if it is in slave mode another device is generating the clock, and a lower rate is required for the XMEGA to sample it.