XMEGA-AU four-port EBI

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I was under impression that the four-port mode was not supported on any of the currently available chips. Apparently it is. There are new registers in the U version that allow to use ports E/F instead of the missing L.

I want non-multiplexed SRAM. Anybody tried that? Any words of wisdom?

EDIT: Well, I tried this on atxmega64a1u on STK600. Without actual SRAM yet. The micro seems to generate all the right signals needed to address up to 16MB of SRAM. That is encouraging.

I wish Atmel would fix the documentation! We need a new version of AVR1312 for the U versions. Need to say something about the EBIOUT in the non-U to U migration guide. The max EBI mode is more like four-and-half-port, rather than just four-port ... unless I'm still missing something.

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How did you enable 4-port EBI configuration? In updated datasheet there is some information about it but it seems to be not correct. E.g. in Atmel Studio, when you choose XMEGA128A1U and run simulator mentioned registers just don’t exists. They don’t exist in io.h file too. So to me 4-port EBI is just a wishlist of Atmel.

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TFrancuz wrote:
How did you enable 4-port EBI configuration?

// Select PORTF as EBI PORT3 and PORTE as chip select outputs
PORTCFG.reserved_0x05 = 3; // EBIOUT
// AVR1312 call
EBI_Enable(EBI_SDDATAW_8BIT_gc,
	     EBI_LPCMODE_ALE1_gc,
	     EBI_SRMODE_NOALE_gc,
	     EBI_IFMODE_4PORT_gc);
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Please let me know if you will be able to run 4-port mode. It’s interesting why Atmel Studio simulator doesn’t support this mode. I don’t think that using reserved registers is a good idea.

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TFrancuz wrote:
Please let me know if you will be able to run 4-port mode. It’s interesting why Atmel Studio simulator doesn’t support this mode. I don’t think that using reserved registers is a good idea.
The register is "reserved" is probably because the toolchain (and the xml files) are just not up-to-date. It is not "reserved" in the datasheet. The simulator is probably the last thing that I would base any conclusions on. As I said in the second part of my original post, everything seems to work just fine, on a real hardware atxmega64a1u, but without an actual SRAM chip yet. So, I'm pretty confident that everything is going to work. I will probably have a board with SRAM in a week or so. We will see.

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Atmel says that simulator is very similar to actual device, even bugs are simulated  I’m talking about Atmel Studio 6.x simulator, not AVR Studio. But we will see. What MCU silicon revision do you have?

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MCU revision - I did not care to look. Will look on Monday. Simulator - well, the register is not listed in the 6.1 xml files either. So, I guess, both the simulator files and the xml files were generated from an older revision of whatever the primary document that they generate everything from. There must be something newer then.

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ezharkov wrote:
MCU revision - I did not care to look. Will look on Monday.
Well, it is L, which appears to be the very first "production" release of 64A1U. The last non-U was H, right? Therefore, the simulator must be running I, J, or K? What MCU.REVID do you see in the simulator?

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Did you get this working? Interested in doing same thing!
Thanks.

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natblist wrote:
Did you get this working?
Yes, in the end it all worked as advertized.

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Hello, sorry for the bump. I'm glad I've found the solution to my long problem! (other than the 16-bit pointer problem and PROGMEM problem)

 

I'm buying this chip. I don't know does this work on an XM128A1U too or just XM64A1U. I need to know what text the chip should have on itself before I buy. I would also want to know is it possible to connect multiple chips. I'm planning to put a SRAM chip and a 8-bit parallel LCD screen on the same EBI. What should the code look like if I would map the SRAM chip's starting address to 0x004000 in XMEGA and have 0xFFxxxx for the screen?

 

Also, how fast is this SRAM mode? I need it to be fast for Uzebox-like tile-based video processing for my parallel TFT LCD 176x200 display.

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Foxcat385 wrote:
I would also want to know is it possible to connect multiple chips. I'm planning to put a SRAM chip and a 8-bit parallel LCD screen on the same EBI.
IIRC all 4 chip selects are available and configurable as either chip selects or additional address bits.

The MattairTech 1MB SRAM XMEGA board shows two chip selects with one of two selected by a jumper.


http://www.atmel.com/devices/ATXMEGA128A1U.aspx?tab=documents (search for AVR1312: Using the XMEGA External Bus Interface)

http://www.mattairtech.com/images/X1/MT-XRAM-1M_schematic_1600.png

"Dare to be naïve." - Buckminster Fuller

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Foxcat385 wrote:
... (other than the 16-bit pointer problem and ...
IAR has a memory model for the XMEGA that covers the entire 16MB data space.

For AVR GCC, Atmel created the Huge Memory package in ASF.

http://asf.atmel.com/docs/latest/xmegaau/html/group__hugemem__group.html

"Dare to be naïve." - Buckminster Fuller

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But IAR is expensive as hell while Atmel Studio is (as much as I was told) worse than ever. It takes so long to install, breaks VS2010 and VS2012 installations. Upon trying to fix it, the patch requires extra files. Pff.... Nightmare. My mentor had trouble with installing VS and Atmel Studio on the school PCs for the next year. The installation of AS took hours! I hope the hugemem can be used without Atmel Studio and with something else like Eclipse. Now can it?

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There is an ASF download though I've yet to try that (it's "huge" wink

Its release notes states use with IDEs other than Atmel Studio.

http://www.atmel.com/tools/avrsoftwareframework.aspx

"Dare to be naïve." - Buckminster Fuller

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Okay.

 

Anyways, I didn't understand this clearly. Did OP use SDRAM with SRAM? From the code, I see that EBI_SDDATAW_8BIT_gc says that SDRAM is used. Then, EBI_LPCMODE_ALE1_gc says that a latch is used. Then, EBI_SRMODE_NOALE_gc says the opposite; NO latch! And finally, EBI_IFMODE_4PORT_gc says that a 4 port mode is used. So is there SRAM or SDRAM or both? Is there a latch? Is this a 4-port or 4.5-port usage? If it's 4.5, then which pin is connected to what? Can someone please draw schematics for me which pin goes where and if I need to use any resistors? I'm definitely confused.

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I just ran into this thread. I used XMEGA128A1U in an industrial project with SRAM with 4-port EBI. Maybe somebody will be still able to use my information.

 

The 4-port mode is working well on this processor. I used this setup:

PORTCFG.EBIOUT = PORTCFG_EBIADROUT_PF_gc | PORTCFG_EBICSOUT_PH_gc;
EBI.CTRL = EBI_SRMODE_NOALE_gc | EBI_IFMODE_4PORT_gc;

EBI.CS2.BASEADDR = 0x0000;
EBI.CS2.CTRLB = EBI_CS_SRWS_1CLK_gc;   // 62,5ns R/W cycle @ 32MHz - you have to meet your SRAM's speed specification
EBI.CS2.CTRLA = EBI_CS_ASPACE_128KB_gc | EBI_CS_MODE_SRAM_gc;

The schematic from my project:

 

How fast is the EBI? The access speed of internal RAM is 2 clock cycles, the max access speed for EBI for 4-port SRAM mode (no multiplexing) is 3 clock cycles, so 2/3 speed of internal RAM. The used SRAM chip has to support this speed!

 

How many chips can be connected? Many. The processor itself has 4 CS signal outputs, so 4 chips without problem. For more chips you have to use some external CS signal generator. The 8-bit bus LCD is also not a problem - you can use one CS output for it and use 2 addresses in that CS range for writing the data to the LCD - one address line connected to RS.

 

Different modes of connecting SRAM and DRAM chips is described in AVR1312: Using the XMEGA External Bus Interface > 2.1 Connecting Memories and Peripherals > 2.1.3 Four-port Interface

 

I wrote about the EBI once, you can find there more information. Let me link it here: Atmel XMEGA with SRAM with 4-port EBI