Xmega ADC limitation

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Hi Guys,

Does the Atxmega128A3 have a 200 ksps sampling limitation for it's internal ADC? If not is it 1 Msps? I read in a thread here that it is 1Msps for 16 bits? Is that true?

Thanks.

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xmega have a 12bit adc with 2msps sampling.

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Ok thanks for the clarification.

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gurra95 wrote:
xmega have a 12bit adc with 2msps sampling.

Unfortunately Atmel always intended this to be the case. One day in the future they may even be able to do it :wink:

At the moment read the datasheet errata. Basically as you increase the speed towards 2Mbps the error rate goes through the window. This is worded differently in the various Xmega datasheets. As the Xmegas all use the same ADC module it is unlikely that they behave differently. Clearly there is a distinct trade off between accuracy and speed. The causeof the problem is not revealed so proceed with care.

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the inaccary is 2LSB+- at 3V as reference and it's lower if the reference is lower.

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gurra95 wrote:
the inaccary is 2LSB+- at 3V as reference and it's lower if the reference is lower.

Not sure where you get that from. According to the main part of the datasheet INL is +/- 5LSB @ 500 ksps.

The errata section then goes on to warn that in differential mode the INL rises to 8LSB @ 2Msps. Go below 0C with a ref of less than 1.3V and its 20LSB. In single ended mode the INL is increased by up to a factor of 3 for the above conditions.

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I want to use the ADC up to 22 kHz (so I need at least 55ksps). Currently I am using Atmega168 which is nowhere close to that (with it's 200 ksps limitation).

I wonder if they used the same architecture that they used in the Mega chips and just beefed up the number of bits (going to a bigger die size) or do they have a flash based design. (I guess the datasheet will give a better explanation; will have to take a look)

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npat_avr wrote:
I wonder if they used the same architecture that they used in the Mega chips and just beefed up the number of bits (going to a bigger die size) or do they have a flash based design.

Hmm... perhaps look at the datasheet before posting the question...

ADC in the XMega could hardly be more different from the one in the ATmega. Read the datasheet/the XMega A manual and application note AVR1300. It is a really impressive piece of technology. Despite my reservations I think Atmel will sort it out in time. Perhaps they were being too ambitous putting this in first generation XMega given all the other changes.

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trevor_g wrote

Quote:

Not sure where you get that from. According to the main part of the datasheet INL is +/- 5LSB @ 500 ksps.

i did get it from the errata section in the datascheet.
Quote:

5. The ADC has up to ±2 LSB inaccuracy
The ADC will have up to ±2 LSB inaccuracy, visible as a saw-tooth pattern on the input voltage/
output value transfer function of the ADC. The inaccuracy increases with increasing
voltage reference reaching ±2 LSB with 3V reference.
Problem fix/Workaround
None, the actual ADC resolution will be reduced with up to ±2 LSB.

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****!!
i did sheck the A1 not A3 datasheet sorry trevor :oops:

[post edited - do not use profanity here - also research answers before posting - the only thing worse than no answer for the OP is a misleading asnwer]

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gurra95 wrote:
****!!

[post edited - do not use profanity here - also research answers before posting - the only thing worse than no answer for the OP is a misleading asnwer]


I tried to tell him the same several times in several forms - to no avail. Seems he's a 14 years sucker abusing his dad's computer just for telling his gibberish anywhere.

Warning: Grumpy Old Chuff. Reading this post may severely damage your mental health.