Xmega A3U I2C STOP signal missing

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Hi,

I', trying to communicate with EEPROM ON-Semicon-ON-CAT24C128WI. I created following program. I order to made easy readable, source code is attached in PDF.

 

 

WP pin on EEPROM is showing 0V, therefore is allowed to write.

 

 

According instruction, after all data are sent for writing, STOP signal is expected and EEPROM will write it inside memory from buffer.

But data are no written (I'm reading FF, which is default value in memory. I tested it also for 100Khz and 400kHz speed. same result, I', seeing START signal (I think) an no data is written.

 

Attaching sequence I2C commands and signal from analyzer. Can please someone to tell me what I'm doing wrong? thx

 

 

 

 

 

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Last Edited: Thu. Oct 24, 2019 - 05:09 AM
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So do you get an ACK when you send the start address?  

Until you get this, nothing will work!

 

Jim

 

 

 

 

 

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Hi Jim,

as per screenshot with I2C sequence, first is "Setup Write to['170'] +ACK", which is respond from device.. actual device address is 0x55. This should indicate, that device respond to the address packet, right?

Last Edited: Wed. Oct 23, 2019 - 07:05 AM
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To be sure, that previous respond wasn't interpreted as answer will put question again here:

this code is relevant:

 

i2c_slave_address_e=I2C_ADDRESS_EEPROM;  //Specifying slave address 0x55
    i2c_slave_address_e<<=1;  //Shift address to left decimal 170
    
    high_eeprom_memory=32;          //Set higher byte for EEPROM access
    low_eeprom_memory=122;        //Set lower byte for EEPROM access

    
    i2c_otvor(I2C_E);                      //Open I2C communication 

 

  Code being executed from library:

/******************************************************

    case 3:
    TWIE.MASTER.CTRLB = TWI_MASTER_SMEN_bm;
    TWIE.MASTER.BAUD = TWI_BAUDSETTING_E;
    TWIE.MASTER.CTRLA = TWI_MASTER_ENABLE_bm;
    TWIE.MASTER.STATUS = TWI_MASTER_BUSSTATE_IDLE_gc;

    TWIE.MASTER.CTRLC=2; //Portrdit citanie
    TWIE.MASTER.STATUS|=TWI_MASTER_RIF_bm|TWI_MASTER_WIF_bm|TWI_MASTER_ARBLOST_bm|TWI_MASTER_BUSERR_bm|TWI_MASTER_BUSSTATE0_bm; //clear all flags initially and select bus state IDLE

    kk=TWIE.MASTER.STATUS;
    kk<<=6;
    while((kk==192) || (kk==128) || (kk==0));
/*******************************************

 

    i2c_rq_zapis(I2C_E); //request write                             Respond from analyzer: Setup Write to ['170'] + ACK

 

  Code being executed from library:

/******************************************************

TWIE.MASTER.ADDR = i2c_slave_address_e+1;
    if(log_level!=0) logovanie(1003,1018,2);
    while(!(TWIE.MASTER.STATUS & TWI_MASTER_RIF_bm));
/********************************************************

 

i2c_zapis(I2C_E,74); //Writing byte with value 74 into memory   Respond from analyzer: J + ACK

 

  Code being executed from library:

/******************************************************

    while((TWIE.MASTER.STATUS & 1) && (TWIE.MASTER.STATUS & 2));
    TWIE.MASTER.DATA = pismeno;       //pismeno=74
    while(!(TWIE.MASTER.STATUS&TWI_MASTER_WIF_bm));
/********************************************************

 

i2c_ukonc(I2C_E); //close I2C

 

  Code being executed from library:

/******************************************************

TWIE.MASTER.CTRLA = TWI_MASTER_ENABLE_bp; //Ukonci I2C
        while(TWIE.MASTER.STATUS & 8);

/********************************************************

 

As per instructruction foer EEPROM, after i2c_zapis(I2C_E,74) STOP signal should be generated but START i generated instead, maybe in i2c_ukonc (Close function) should be changed something? Or I some other instruction should be added?

I tried follow code, but it didn't do:

TWIF.MASTER.CTRLC |= 3

 

But in debugging mode I checked register, no change. So question is, what I'm missing?

 

 

    
  

Last Edited: Fri. Oct 25, 2019 - 06:57 AM
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I found out, that after command:

 

TWIE_MASTER_CTRLC|=3;

 

STOP will occur but I need to wait at least 26 uS to continue (attachment from analyzer). Can somebody please tell me how I can test that STOP happened?

 

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You should be able to just send a start, followed by a stop and see that on your I2C analyzer.

Most eproms have a sequence like:

start read followed by eeprom address (where you want to write data)

restart write

eeprom data ( repeat as needed)

stop

 

What eeprom are you using?  can you provide link to datasheet?

 

Jim

 

 

 

 

 

Last Edited: Fri. Oct 25, 2019 - 06:23 PM
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Hi Jim,

I'm seeing STOP on analyzer (previous attached screenshot is showing it), but STOP will only happen, if there is delay after instruction:

 

TWIE_MASTER_CTRLC|=3;

 

Otherwise stop won't occurred if there is followed by another I2C instruction. Obviously I don't want to solve it by inserting delay but rather to detect that STOP happened.

 

EEPROM IS CAT24C128WI

 

https://www.onsemi.com/pub/Colla...

 

Thx

 

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Thanks for the DS link, Normally when the master writes, there is no delay after the slave ACK's and the master can send stop at any time.....

 

But when data is read from the slave, the master ACK's each byte until the last one, then the master must NAK, so the slave will stop sending and release the bus so the master can send stop.

if the NAK is not sent (i.e. an ACK is sent) then the master can not send stop as the bus is busy by the slave.  This is seen as a bus error and some times a time out has to happen in order

to reset the bus.  

Is this what your seeing?   The solution is to send NAK when the master is done reading all the data it wants.

Jim

 

 

 

 

 

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This is sequence of I2C instructions (From analyzer):

 

Setup Write to ['170'] + ACK      //Sending Slave address together with bit setup for reading
' ' + ACK                                    //Writing 1 byte with first part of memory address
z + ACK                                     //Writing 1 byte with second part of memory address
J + ACK                                     //Writing value to be added to memory

 

According to memory manual, value will be only in cache, in order to write it inside memory space, STOP signal need to be generated

 

So in code I have this

 

TWIE_MASTER_CTRLC|=3; //stop code

 

But when is immediately follow by closing I2C connection, apparently there is not enough time to execute. As per screenshoot attached it need around 26uS to execute (time between sending "J" and putting STOP on link). and since my processor is on 32Mhz,

executing instructions for closing I2C is much faster than TWI system can send STOP. So before closing I need somewhow to detect that STOP was executed on TWI link. I'm running I2C on 100Khz, on 1MHz time is only 6uS, but still to long.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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jozefvelky wrote:
I need somewhow to detect that STOP was executed on TWI link.

YOu should be able to get this by polling the twi status reg, bus state bits...

 

Jim

 

 

 

 

 

 

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Hi Jim,

mystery solved. As per datasheet, write time is up to 5ms, but slave not indicated when is done. Therefore after sending STOP signal I added delay 5ms and now working well. Also 64 byte cache, where data are written

before moving to memory space is aligned with memory page. EG. if you writing 32 bytes if beginning is let's say 20 bytes before end of page, only 20 bytes will be written.

 

I conludding problem as resolved, Thx for all you help.