I've seen that people append two NOPs after setting the GM mask in the SR on the AVR32-UC3.
Probably to clear the instruction pipeline to make sure interrupts are really disabled.
Absolutely, pipeline seems implicated here, but I still don't quite understand whether the two NOPs are absolutely necessary and if it is wrong not to have them.
I mean, the ASF built-in function for disabling interrupts cpu_irq_disable() does NOT generate the two NOPs, as I verified by looking at the disassembly window.
So, which way is it. Shall I use the two NOPs just for good measure, because "that is how it's done"?
How do you guys disable interrupts?
Two NOPs were needed on early versions of the UC3 devices due to a hardware bug. This has been fixed in newer hardware revisions.
Letting the smoke out since 1978
Could this relate to the probable processor bug I found?
The faulty situation here apparently usually comes after three or four nops from the interrupt disable though. The exact specification of the part we use is (as printed on the UC's surface):
You should contact Atmel about that, they know exactly what those numbers mean.
I did. Almost two weeks ago... (See the topic with the bug, I posted an update there)
I would guess no. I believe this bug was fixed in the UC3A and the UC3B well before the UC3C came out.
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