Why interupt affect loading from program memory?

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it is snapped from data sheet ?

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Google instruction pipeline

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I know That the avr micro controller that i am using now  is single pipeline due to the architecture of harvard  

what is the relation of pipeline ?

 

I am living to bring up new earth ,and not to eat and destroy earth.

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Mohamed asaad wrote:

I know That the avr micro controller that i am using now  is single pipeline due to the architecture of harvard  

 

No, it's Modified Harvard because you can access program as if it were data. But I wouldn't get too worried about what 'type' of architecture it is; it tends to be a pointless discussion in anything other than academic research.

 

And you can have a pipeline, or not, in any type of architecture.

#1 This forum helps those that help themselves

#2 All grounds are not created equal

#3 How have you proved that your chip is running at xxMHz?

#4 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand." - Heater's ex-boss

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but this was a reply for the main question what is the relation between interrupt affect loading from program memory and  pipeline ?

 

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Hang on, we're talking xmega here aren't we?

 

AFAIK, on the xmega, the LD instruction cannot load data from the flash space as it is not memory mapped.

 

If you look at the whole of that footnote...

 

 

..you will see that note 2 does not apply to xmegas.

#1 This forum helps those that help themselves

#2 All grounds are not created equal

#3 How have you proved that your chip is running at xxMHz?

#4 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand." - Heater's ex-boss

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Since you posted the same question in the UC3 section, can we start by clarifying which chip family we are talking about.

#1 This forum helps those that help themselves

#2 All grounds are not created equal

#3 How have you proved that your chip is running at xxMHz?

#4 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand." - Heater's ex-boss

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i am only asking the question how it happened 

i read it and i wondered 

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Remember - we didn’t design the chip, so we can only infer what might happen.
Historically, interrupts are usually sampled before an intruction fetch. With pipelines, the picture changes as a fetch might be done in parallel with an instruction issue. If an interrupt is pending, then the pipeline might need to be flushed maybe incurring a 1cycle penalty. This is speculation on my part as i’ve not used an xmega part nor looked into its microarchitecture.