I'm trying to figure out how much data I can feed into a micro-controller before I need to start worrying about flow control. I'm using an ATMEGA324A, which has a "Data Overrun" bit in the control and status register, but I don't understand when it is set. The datasheet says
This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive
buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. This bit is valid until the receive buffer (UDRn) is read.
I've underlined the sentence that is giving me trouble. In particular the "it is" doesn't make any sense to me. If I were to make it "there is" (or just remove the "it is") I can make sense of the sentence. It would say that if I was transmitting data to the micro-controller without ever reading UDR then I would expect the chain of events to look like this:
1) The first byte is received and put into the buffer (UDR)
2) The 2nd byte is received and put into the buffer (UDR, but inaccessible in the FIFO till byte 1 is read)
3) The 3rd byte is received and stays in the receive shift register.
4) The start bit of the 4th byte triggers the data overrun condition.
Is that what happens? If you start with an empty buffer it's the start of the 4th byte that triggers the overrun?