Weird software reset problem while waiting for DMA is done

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hey guys,

i'm currently trying to use DMA for my ADC conversions.

But i got a problem when i'm waiting for the DMA is done with the whole transaction.

It start at the beginnen after a few time going to the while (wait) loop.

 

Only if i step through the while loop by hand it doesn't reset :/. And if i let is run to the next breakpoint it resets.(which is directly after the while loop)

 

do{
			puts("waiting");
			delay_ms(10);
		}while (!(DMA.INTFLAGS & DMA_CH3TRNIF_bm));
		DMA.INTFLAGS = DMA_CH3TRNIF_bm;
		printf("DMA works ! %d offset\r\n", offset);
void dma_init(void){
	/*// reset DMA controller
	DMA.CTRL = 0;
	DMA.CTRL = DMA_RESET_bm;
	while ((DMA.CTRL & DMA_RESET_bm) != 0);
	// configure DMA controller
	DMA.CTRL = DMA_CH_ENABLE_bm | DMA_DBUFMODE_DISABLED_gc; // single buf channel 3
	
	// channel 3
	// **** TODO: reset dma channels
	DMA.CH3.REPCNT = 0;
	DMA.CH3.CTRLA =		DMA_CH_BURSTLEN_2BYTE_gc | DMA_CH_SINGLE_bm | DMA_CH_REPEAT_bm; // ADC result is 2 byte 12 bit word
	DMA.CH3.ADDRCTRL =	DMA_CH_SRCRELOAD_BURST_gc | DMA_CH_SRCDIR_INC_gc | // reload source after every burst
						DMA_CH_DESTRELOAD_TRANSACTION_gc | DMA_CH_DESTDIR_INC_gc; // reload dest after every transaction
	DMA.CH3.TRIGSRC =	DMA_CH_TRIGSRC_ADCB_CH3_gc;
	DMA.CH3.TRFCNT =	SAMPLE_COUNT*2; // always the number of bytes, even if burst length > 1
	DMA.CH3.DESTADDR0 = (( (uint16_t) adcSamples) >> 0) & 0xFF;
	DMA.CH3.DESTADDR1 = (( (uint16_t) adcSamples) >> 8) & 0xFF;
	DMA.CH3.DESTADDR2 = 0;
	DMA.CH3.SRCADDR0 =	(( (uint16_t) &ADCB.CH3.RES) >> 0) & 0xFF;
	DMA.CH3.SRCADDR1 =	(( (uint16_t) &ADCB.CH3.RES) >> 8) & 0xFF;
	DMA.CH3.SRCADDR2 =	0;*/

//Upper part is commented because i wanted to see if it was because of my own code
	#define DMA_CHANNEL 3
	struct dma_channel_config config;
	
	memset(&config, 0 , sizeof(config));
	dma_channel_set_burst_length(&config, DMA_CH_BURSTLEN_2BYTE_gc);
	dma_channel_set_transfer_count(&config, SAMPLE_COUNT*2);
	dma_channel_set_repeats(&config, 0);
	dma_channel_set_src_reload_mode(&config, DMA_CH_SRCRELOAD_BURST_gc);
	dma_channel_set_dest_reload_mode(&config, DMA_CH_DESTRELOAD_TRANSACTION_gc);
	dma_channel_set_src_dir_mode(&config, DMA_CH_SRCDIR_INC_gc);
	dma_channel_set_dest_dir_mode(&config, DMA_CH_DESTDIR_INC_gc);
	dma_channel_set_source_address(&config, (uint16_t)&ADCB.CH3RES);
	dma_channel_set_destination_address(&config, (uint16_t)adcSamples);
	dma_channel_set_trigger_source(&config, DMA_CH_TRIGSRC_ADCB_CH3_gc);
	dma_channel_set_single_shot(&config);
	
	dma_enable();
	dma_channel_write_config(DMA_CHANNEL, &config);
	dma_channel_enable(DMA_CHANNEL);

}

The DMA function works. I tried it in a different project with only my ADC and DMA. But i my main project it resets.

The reset doens't occur when the while loop is taken out for the DMA.

The reset flags arent't set and got no watchdog.

Is there some time-out for the program or is it something else.

 

[EDIT:]

I do enable both ADC and DMA.

enable_ADC();

DMA.CH3.CTRLA |= DMA_ENABLE_bm;

The weird part is that alle the initialisations for T/C, SPI, TWI and stuff are done or kept in the registers after the "reset".

 

The program tries to run all the initialisations, but because of some weird things. The program doesn't call the ISR's for TWI or other ones. The flag are set to go to the ISR and the SREG I flags is enabled. So it should go to the ISR :/

It isn't any different from the first initialisation.

This topic has a solution.
Last Edited: Tue. May 12, 2015 - 08:50 AM
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It seems that the Reset occures when the program is in a ISR. 

So the PMIC.Status register says it is still executing a ISR, when the program begin from the beginning again.

 

This maybe the problem that the ISR won't run after the weird "reset".

 

Anyone got an idea how to prevent this or how to clear the register?

This reply has been marked as the solution. 
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Do you enable, for example, ADC interrupt without providing an ISR?

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Hey thx for the reply,

 

By saying that about the ISR. I checked again if i did disabled all the other ISR's. There was one that i forgot somewhere in 1 line.

 

Thanks