AVR Freaks

clawson, thanks for the link.  Its unclear from that if WDT is supported or not in the simulator, but if I can get past that problem, then working out stimulus files was my next challenge and that information is there, so thanks.

    ; Write signature for change enable of protected I/O register
    set_io      CCP, 0xD8                       ; Allow change of protected registers.
  9e:	08 ed       	ldi	r16, 0xD8	; 216
  a0:	0c bf       	out	0x3c, r16	; 60
    ; Within four instruction cycles, Configure Clock Prescaler.
    set_io      CLOCK_PSR, CLOCK_8MHZ           ; Set Clock Prescaler to 8Mhz (1Mhz is default)
  a2:	f6 bf       	out	0x36, r31	; 54
    ; Within four instruction cycles, Configure WDT
    set_io      WDTCSR, ((1<<WDIE) | 0x06)      ; Interrupts ONLY, AND 1 Second Interval.
  a4:	06 e4       	ldi	r16, 0x46	; 70
  a6:	01 bf       	out	0x31, r16	; 49
    wdr                                         ; Start Watchdog counting from 0.
  a8:	a8 95       	wdr

There is the code to initialise the watchdog, I am aware of the special write to the CCP to enable writes to protected registers which can only happen up to 4 cycles later, the WDTCSR is written 3 cycles after that. Interrupts are disabled during this initialisation, so no ISR can trigger during this time to upset the timing.

r31 is pre-initialised to 0x00 earlier in the code.

Apologies for not just putting the source code, but its a GCC Assembler program and I use both GAS macros and C Preprocessor statements extensively, so it wouldn't look like real assembler, and then I would have to explain why i wrote the macros like I have, etc etc.  The Dump above shows the actual assembled instructions with my code interspersed, the only thing that really matters are the CPU instructions.

I do call SEI later in the code, and then spin in a loop waiting for the Watchdog Timer tick.

    ; Lastly Enable Interrupts
    sei                                         ; Enable Interrupts after configuration
  fc:	78 94       	sei

000000fe <main>:
.global main
main:

    ; Wait until a ONE WIRE RESET is detected.
wait_for_bus_reset:
    rjmp        wait_for_bus_reset              ; Loop here, waiting for OW Comms Reset Pulse
  fe:	ff cf       	rjmp	.-2      	; 0xfe <main>

There is a Watchdog Timer ISR routine, AND I put breakpoints on every possible vector of the CPU while waiting for the Tick, and nothing ever triggers (including reset), and when I break its spinning on my loop.  I have waited for many minutes and never had the WDT trigger.  I have seen the Timer0 Counter monotonically increase and wrap in the simulator, so its not running too slowly. I have timed and I am getting approximately 271,585 simulated CPU cycles per second, so while not realtime, certainly fast enough for my debugging needs.  I have other possible sources of interrupt in my program, but they require stimulus on pins to trigger them or set them up and there is no stimulus yet, so the only possible IRQ source at the moment is the WDT.

The simulator shows the I bit in SREG set, specifically, SREG = 0x82 (I and Z) when spinning on my loop.  The loop is simply a rjmp to itself, there is no other processing so SREG is not changing at all while waiting.

I was really hoping for a good simulation of the ATTiny9 because it has no debug capability and such limited IO, that I don't have any available for debug status (and certainly no code space for anything more sophisticated than set a pin, clear a pin, in any event). 

Simulation seemed the only real way to test the code.  I have written the assembly code in such a way that i can rebuild the program and run it on a atmega328p which is very different, but is largely a peripheral superset of the attiny9.  However, I know that emulating on a different MCU is not ideal (remembering back to working with In-circuit emulators on MC68302). I may have little choice however, especially if one of my two timers is unavailable in the simulator.

The code is built with AtmelStudio 7.0.1417, so whatever version of the Simulator, GCC/GAS/LD, etc that is shipping with.