AVR Freaks

-- Calvert #5
-- EET3254
-- two digit counter, counts at 1 second intervals
-- only counts when power is high
-- if clear goes low when power is low, it will reset the count
-- common cathode displays are used
-- clock = 1843200 hz

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity calvert5 is
    Port ( power : in boolean;
    		 clear : in boolean;
    		 clock : in std_logic;
           ones : out std_logic_vector(6 downto 0);
           tens : out std_logic_vector(6 downto 0));     
end calvert5;

architecture Behavioral of calvert5 is
signal onesdigit : integer range 0 to 9;
signal tensdigit : integer range 0 to 9;
signal count : integer range 0 to 1843200;
begin
	process(clock, power, clear, tensdigit, onesdigit) begin
		if power then
			if rising_edge(clock) then
				count <= count + 1;
				if count = 1843200 then	-- one second has passed
					if onesdigit = 9 then  -- a rollover needs to occur
						if tensdigit = 9 then  -- rollover both digits
							onesdigit <= 0;
							tensdigit <= 0;
						else
							onesdigit <= 0;  -- rollover ones digit
							tensdigit <= tensdigit + 1;  -- increment tens
						end if;
					else
						onesdigit <= onesdigit + 1;  -- increment ones digit
					end if;
				end if;
			end if;
		elsif not power and not clear then
			onesdigit <= 0;  -- conditions have been met to clear counter
			tensdigit <= 0;
		end if;
		
		-- seven segment decoder for ones digit			
		case onesdigit is
			when 0 =>	-- 0
				ones <= "1111110";
			when 1 =>	-- 1			
				ones <= "0110000";
			when 2 =>	-- 2
				ones <= "1101101";
			when 3 =>	-- 3
				ones <= "1111001";
			when 4 =>	-- 4
				ones <= "0110011";
			when 5 =>	-- 5
				ones <= "1011011";
			when 6 =>	-- 6
				ones <= "1011111";
			when 7 =>	-- 7
				ones <= "1110000";
			when 8 =>	-- 8
				ones <= "1111111";
			when 9 =>	-- 9
				ones <= "1110011";
			when others =>
				ones <= "0000000";
		end case;

		-- seven segment decoder for tens digit
		case tensdigit is
			when 0 =>	-- 0
				tens <= "1111110";
			when 1 =>	-- 1			
				tens <= "0110000";
			when 2 =>	-- 2
				tens <= "1101101";
			when 3 =>	-- 3
				tens <= "1111001";
			when 4 =>	-- 4
				tens <= "0110011";
			when 5 =>	-- 5
				tens <= "1011011";
			when 6 =>	-- 6
				tens <= "1011111";
			when 7 =>	-- 7
				tens <= "1110000";
			when 8 =>	-- 8
				tens <= "1111111";
			when 9 =>	-- 9
				tens <= "1110011";
			when others =>
				tens <= "0000000";
		end case;
		
	end process;	 

end Behavioral;

module Port (power, clear, clock, ones, tens);

input	power,
	clear,
	clock;

output	[6:0]	ones,
		tens;



// =-=-=-=-=-=-=-=-=--

reg	[0:3]	onesdigit,	// counts to 9
		tensdigit;	// counts to 9

	// did not figure out exact bit size needed here.
reg	[23:0]	count;		// must count to 1C2000h (1843200)

always @ (posedge clock)
begin
  if (power)
   begin
     count <= (count + 1);
     if (count == 1843200)
      begin
	if (onesdigit == 9)
	 begin
	   if (tensdigit == 9)
	    begin
	      onesdigit <= 0;			// rollover both digits
	      tensdigit <= 0;
	    end					// if tensdigit == 9
	   else
	    begin
	      onesdigit <= 0;			// rollever ones digit
	      tensdigit <= (tensdigit + 1);	// inc tens
	    end
	 end
	else					// if onesdigit == 9
	 onesdigit <= (onesdigit + 1);		// increment ones digit
      end

     else					// if power
      begin
	if (!clear)
	 begin
	   onesdigit <= 0;
	   tensdigit <= 0;
	 end
      end
   end						// end of if power begin..end

   //   -- seven segment decoder for ones digit
   case (onesdigit)
      0:  ones <= 7'b1111110;
      1:  ones <= 7'b0110000;
      2:  ones <= 7'b1101101;
      3:  ones <= 7'b1111001;
      4:  ones <= 7'b0110011;
      5:  ones <= 7'b1011011;
      6:  ones <= 7'b1011111;
      7:  ones <= 7'b1110000;
      8:  ones <= 7'b1111111;
      9:  ones <= 7'b1110011;

      default: ones <= 7'b0000000;

   endcase

   //   -- seven segment decoder for tens digit
   case (tenssdigit)
      0:  tens <= "1111110;
      1:  tens <= "0110000;
      2:  tens <= "1101101;
      3:  tens <= "1111001;
      4:  tens <= "0110011;
      5:  tens <= "1011011;
      6:  tens <= "1011111;
      7:  tens <= "1110000;
      8:  tens <= "1111111;
      9:  tens <= "1110011;

      default: tens <= 7'b0000000;

   endcase
end

endmodule