VHDL beginner

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Hi guyzz

I just got a XILINX XC95108 CPLD Development Kit and an
Altera MAX7000 devel board.

Now i have to do somethings with them :oops:

I bought them because i would like to try some CPLD/FPGA , ie make some input output to an AVR etc..

I have downloaded the ISE WebPack and have looked a little at it :)

I found this site describing some VHDL

http://www.amontec.com/fix/vhdl_...

And was wondering if its of any usr for a total beginner like me :?

/Bingo

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This is a fairly large step but it can be a lot of fun. I can't help you much with VHDL; I've tried several times to warm up to it without much success. The only Hardware Description Language that I learned was Verilog but it works well with both Xilinx and Altera toolsets.

An HDL will allow you to describe the operation of the circuitry that you intend to implement - in an ASIC, FPGA, CPLD or whatever. You are literally writing hardware. And, just as with simulators that you can use to check your software before you download it to Flash, there are Verilog (and VHDL) simulators that allow you to observe the operation of your circuitry or use a testbench to stimulate it. Once you are happy with circuit operation in the HDL, the vendor tools will compile the design for the target device. Many of the simulator tools used to be quite expensive, but I see that there are now many open source alternatives that should help get you going. This is a really fun area, but it's also quite complex.

Dave

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Thank you for the input Dave

Not that im ready for this

http://members.optushome.com.au/...

But i wrote my first C program using Introl-C on a Flex 6809 Computer
And btw also my first assembler program , wayyyy back , in pre historic time , where 8K Static ram with 2114's was a lot , and another 48K using 4116 was huuggge, and first 90K on a floppy , then "drill the index hole trick" and use the other side of the floppy on the single sided floppydrive.

Compiling meant swapping floppy 3 or 4 times , by hand :D :D

It sure does bring back memories

Well back to VHDL ..

Does anyone have a link to a basic howto with one of the above CPLD's

I mean i have the boards , a programmer/Jtag for each but i would love to get my hands on a "Make the LED Blink" guide :lol: :lol: (Im using XP , but have a cpl. of Redhat 9.0's also)

If anyone know a Course/NightSchool here in DK where i can join please feel free to give a hint ..

/Bingo

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Well, if you can't be turned from the VHDL darkside...

http://www.xess.com/pragmatic-2_1.html

They have a tutorial you can download along with lots of VHDL examples. This is for Xilinx, but would apply to Altera as well.

BTW, I remember the Flex 6809 (SWTPC) well - it was the first commercial computer I owned. I once spent a couple of weeks hand disassembling the 2K monitor program to see how a disk operating system worked. Those were the days.

Dave

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I've program several Xilinx 95108's without VHDL. Instead I use the schematic tool in the Xlinix ISE and layout the CPLD using logic symbols. You might give that a shot.

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Is that like making a schematic using TTL's :?: :?:

/Bingo

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Sometimes it's faster to use the integrated circuit editor to describe the functions. But i can remeber a project where i was not able to design a working circuit and the problem was solved with about 25 lines of VHDL code. If you want to pack a existing circuit into the CPLD use the circuit tool. If you want to feel the power of CPLD's ( & FPGA's) use VHDL to descibe the functions.

Hava a look at my web page -> http://www.tobiscorner.at.tf

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bingo, here is a piece of VHDL code due for one of my classes. yes, it works! :shock:

-- Calvert #5
-- EET3254
-- two digit counter, counts at 1 second intervals
-- only counts when power is high
-- if clear goes low when power is low, it will reset the count
-- common cathode displays are used
-- clock = 1843200 hz

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity calvert5 is
    Port ( power : in boolean;
    		 clear : in boolean;
    		 clock : in std_logic;
           ones : out std_logic_vector(6 downto 0);
           tens : out std_logic_vector(6 downto 0));     
end calvert5;

architecture Behavioral of calvert5 is
signal onesdigit : integer range 0 to 9;
signal tensdigit : integer range 0 to 9;
signal count : integer range 0 to 1843200;
begin
	process(clock, power, clear, tensdigit, onesdigit) begin
		if power then
			if rising_edge(clock) then
				count <= count + 1;
				if count = 1843200 then	-- one second has passed
					if onesdigit = 9 then  -- a rollover needs to occur
						if tensdigit = 9 then  -- rollover both digits
							onesdigit <= 0;
							tensdigit <= 0;
						else
							onesdigit <= 0;  -- rollover ones digit
							tensdigit <= tensdigit + 1;  -- increment tens
						end if;
					else
						onesdigit <= onesdigit + 1;  -- increment ones digit
					end if;
				end if;
			end if;
		elsif not power and not clear then
			onesdigit <= 0;  -- conditions have been met to clear counter
			tensdigit <= 0;
		end if;
		
		-- seven segment decoder for ones digit			
		case onesdigit is
			when 0 =>	-- 0
				ones <= "1111110";
			when 1 =>	-- 1			
				ones <= "0110000";
			when 2 =>	-- 2
				ones <= "1101101";
			when 3 =>	-- 3
				ones <= "1111001";
			when 4 =>	-- 4
				ones <= "0110011";
			when 5 =>	-- 5
				ones <= "1011011";
			when 6 =>	-- 6
				ones <= "1011111";
			when 7 =>	-- 7
				ones <= "1110000";
			when 8 =>	-- 8
				ones <= "1111111";
			when 9 =>	-- 9
				ones <= "1110011";
			when others =>
				ones <= "0000000";
		end case;

		-- seven segment decoder for tens digit
		case tensdigit is
			when 0 =>	-- 0
				tens <= "1111110";
			when 1 =>	-- 1			
				tens <= "0110000";
			when 2 =>	-- 2
				tens <= "1101101";
			when 3 =>	-- 3
				tens <= "1111001";
			when 4 =>	-- 4
				tens <= "0110011";
			when 5 =>	-- 5
				tens <= "1011011";
			when 6 =>	-- 6
				tens <= "1011111";
			when 7 =>	-- 7
				tens <= "1110000";
			when 8 =>	-- 8
				tens <= "1111111";
			when 9 =>	-- 9
				tens <= "1110011";
			when others =>
				tens <= "0000000";
		end case;
		
	end process;	 

end Behavioral;

I dont really know how helpful this will be for you, but its a pretty simple example of VHDL code and how things can be done. VHDL is kinda quirky, but it can be very powerful if used correctly. The Xilinx Web Pack ISE leaves you out to dry on some occasions though. If you have specific questions I would be glad to answer them if I can. Good luck!

Last Edited: Wed. Sep 29, 2004 - 12:13 AM
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Hi,

If you are starting with VHDL IMHO you really need a book. "VHDL For Programmable Logic" was quite good I found, and would be directly applicable.

"VHDL Starter's Guide" is also a good read, though does not target programmable logic at all and more discusses simulation aspects. if you had only one of them I'd go with the "VHDL for Programmable Logic".

-Colin
[/list]

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Hi. I know from practise that Verilog is much useful than VHDL is. I'am using it for 2 years.I'am using Altera APEX and Cyclone FPGAs. Difference between VHDL and Verilog is like difference between assembler and C. On Altera's APEX I did 32 channels DTMF decoder and 32 channels FSK (CLIP) decoder and much more.All in one chip. Good Luck!!!

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Bingo600 wrote:
Thank you for the input Dave

Not that im ready for this

http://members.optushome.com.au/...

But i wrote my first C program using Introl-C on a Flex 6809 Computer
And btw also my first assembler program , wayyyy back , in pre historic time , where 8K Static ram with 2114's was a lot , and another 48K using 4116 was huuggge, and first 90K on a floppy , then "drill the index hole trick" and use the other side of the floppy on the single sided floppydrive.

Compiling meant swapping floppy 3 or 4 times , by hand :D :D

It sure does bring back memories

Well back to VHDL ..

Does anyone have a link to a basic howto with one of the above CPLD's

I mean i have the boards , a programmer/Jtag for each but i would love to get my hands on a "Make the LED Blink" guide :lol: :lol: (Im using XP , but have a cpl. of Redhat 9.0's also)

If anyone know a Course/NightSchool here in DK where i can join please feel free to give a hint ..

/Bingo

I've got a 'getting started' web page for CPLDs here:

http://www.geocities.com/leon_he...

Leon

Leon Heller G1HSM

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I would not even try to learn VHDL. In general, it takes double the size to accomplish something. There is alot of overhead you need to write.

The language was designed for the Military.

Try Verilog, here is Ezcomp's code in Verilog but not verified against syntax errors!

module Port (power, clear, clock, ones, tens);

input	power,
	clear,
	clock;

output	[6:0]	ones,
		tens;



// =-=-=-=-=-=-=-=-=--

reg	[0:3]	onesdigit,	// counts to 9
		tensdigit;	// counts to 9

	// did not figure out exact bit size needed here.
reg	[23:0]	count;		// must count to 1C2000h (1843200)

always @ (posedge clock)
begin
  if (power)
   begin
     count <= (count + 1);
     if (count == 1843200)
      begin
	if (onesdigit == 9)
	 begin
	   if (tensdigit == 9)
	    begin
	      onesdigit <= 0;			// rollover both digits
	      tensdigit <= 0;
	    end					// if tensdigit == 9
	   else
	    begin
	      onesdigit <= 0;			// rollever ones digit
	      tensdigit <= (tensdigit + 1);	// inc tens
	    end
	 end
	else					// if onesdigit == 9
	 onesdigit <= (onesdigit + 1);		// increment ones digit
      end

     else					// if power
      begin
	if (!clear)
	 begin
	   onesdigit <= 0;
	   tensdigit <= 0;
	 end
      end
   end						// end of if power begin..end

   //   -- seven segment decoder for ones digit
   case (onesdigit)
      0:  ones <= 7'b1111110;
      1:  ones <= 7'b0110000;
      2:  ones <= 7'b1101101;
      3:  ones <= 7'b1111001;
      4:  ones <= 7'b0110011;
      5:  ones <= 7'b1011011;
      6:  ones <= 7'b1011111;
      7:  ones <= 7'b1110000;
      8:  ones <= 7'b1111111;
      9:  ones <= 7'b1110011;

      default: ones <= 7'b0000000;

   endcase

   //   -- seven segment decoder for tens digit
   case (tenssdigit)
      0:  tens <= "1111110;
      1:  tens <= "0110000;
      2:  tens <= "1101101;
      3:  tens <= "1111001;
      4:  tens <= "0110011;
      5:  tens <= "1011011;
      6:  tens <= "1011111;
      7:  tens <= "1110000;
      8:  tens <= "1111111;
      9:  tens <= "1110011;

      default: tens <= 7'b0000000;

   endcase
end

endmodule

Regards

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talking about VHDL, i heard from a friend that SYSTEM-C is good. its like VHDL programmed in C++, all the syntax are C++ based, only its used for hardware design. i haven't explored this yet but heard that its competing VHDL. anyone have a comment on this?
:twisted:

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Seems like i'd better start with Verilog or the schematic approach.

And maybe buy the book Colin suggested

But it seems like i need a clock circuit first , the boards i have have no clock generator on them.

The examples i have seen needs TTL clock is that correct ??

Where is my 1000 Oscillators ??

Hmmm....

I could use my mega32 to run a clock for the board on a toggle pin :lol:

/Bingo

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An oscillator inside a digital circuit would be really an analog circuit most likely with some capacitors, resistance and some logic gates (in simplest terms).

You will always need a clock signal to do clocked logic.

You can do simpler things like combinatorial logic without a clock but you can't latch the output without somekind of a clock.

you could say: assign a = c & b; in Verilog

a then equals c AND b;

Regards

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Bingo,

Don't be put off by other people's preferences. You can have a look at all approaches and see which one fits you. They each have their pros and cons as with any thing else.

Have a look here for a starter. http://www.doulos.com/knowhow/ I would recommend their courses, but they are not cheap.

Best of luck.

Sacha.