Couldn't find any info on this. Taken from the ATMEGA328P data sheet:
A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The CPU can load the
transmit buffer by writing to the UDRn I/O location. The buffered data in the transmit buffer will be moved to the
Shift Register when the Shift Register is ready to send a new frame. The Shift Register is loaded with new data if it
is in idle state (no ongoing transmission) or immediately after the last stop bit of the previous frame is transmitted.
When the Shift Register is loaded with new data, it will transfer one complete frame at the rate given by the Baud
Register, U2Xn bit or by XCKn depending on mode of operation.
Looking at this bit:
The Shift Register is loaded with new data if it is in idle state (no ongoing transmission)
When first writing to UDR, the Shift Register will be empty, therefore upon UDR receiving a byte I'm guessing it will "immediately" pass the data to the shift register, then UDR is ready to receive another byte and the UDRE0 (USART Data Register Empty flag) will be set again.
If UDRIE0 (USART Data Register Empty Interrupt Enable 0) is set then the corresponding ISR will fire again after a very short time, or perhaps immediately. I'm guessing UDR could transfer the data into the empty shift register and have the UDRE0 bit set again by the time the ISR finished. Therefore my variable value which gets passed to UDR would not have changed.
I'm sending a stream of bytes using an UDRIE0 ISR but the very first byte is being transmitted twice. My >>guess<< of what is happening is that my code has not had a chance to increment the send byte because the 2nd ISR is being triggered immediately after the 1st.
In contrast the time gap between the 2nd and 3rd ISR run and subsequent runs will have a time gap of about 16,666 clock cycles (9600 baud, 16Mhz clock, 10 data bits in packet) while the shift register is emptying, so after returning from the ISR my code has years to increment the value to be sent.
Hope that all made sense,