USART and MPCM

Go To Last Post
8 posts / 0 new
Author
Message
#1
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

My ATmega8 data sheet (Dec 2002), on page 147, says:

Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCM bit. The MPCM bit shares the same I/O location as the TXC flag and this might accidentally be cleared when using SBI or CBI instructions.

OK, since SBI and CBI each take 2 cycles, if the cpu sets TXC between the 2 cycles, the flag could be lost. If it was already set it should be preserved.

I don't see an alternative that avoids this possibility. If I simply do an OUT to UCSRA, since TXC and MPCM are both writable bits, I would destroy the TXC information already there. If I test for TXC before the OUT there will still be one (or more) cycles before the the register is written, so this is no better than SBI and CBI.

Have I missed something?

Laurence Boyd II

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Would this sequence work: [untested]

cli
in myreg, ucsra
ori myreg, (1 << mpcm)
out ucsra, myreg
sei

I guess the question is: will the TXC flag get set, even with interrupts disabled?

Lee

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

the TXC flag can only be set by hardware and to clear it with software you write 1 to it. That means you should always make sure that the TXC bit is 0 when writing to the register (unless you really want to clear it).

-Geir

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I believe the TXC flag is set regradless of wheither interrupts are enable or not, since one tests this flag when not using interrupts. If the above sequence would eliminate the possiblity then why should not the following also, contrary to the note?

cli
sbi ucsra,(1 << mpcm)
sei

Laurence Boyd II

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

In practical use, the key might be in this excerpt from Mega8 datasheet:

"The TXC Flag is useful in half-duplex communication interfaces (like the RS485 standard), where a transmitting application must enter Receive mode and free the communication bus immediately after completing the transmission."

Thinking about this, I would tend to use this type of communication in a half-duplex environment, anyway. In that case, one would wait for TXC >>before<< flipping back to MPCM. So the question/problem would be moot.

If full-duplex is needed, I guess that the code sequence would have to look at TXC after reading UCSRA and set the "TXC-found-flag" for later processing.

I'm trying to think of a case where, if TXCIE is set, the bit would actually be overwritten. It would be if the OUT instruction is the current instruction with TXC set. But wouldn't the interupt be pending then? Or does the waiting interrupt "go away" when TXC is written?

Makes my head hurt. But I can't see a problem in half-duplex.

Lee

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I think you have misunderstood the problem. The sbi/cbi issue has nothing to do with interrupts. The problem is that if you use sbi or cbi you read the register, set or clear the bit position specified and write the content back. It does exactly what Lee suggest (for sbi):

in myreg, ucsra
ori myreg, (1 << mpcm)
out ucsra, myreg

The only difference is that sbi is a one word/two cycles instruction.

What happens if you use the above instructions or sbi when the TXC is set? You write back a one to TXC, and clear the flag (regardless of which bit position you set/clear). The correct instruction sequence for correct operation would be:

in myreg, ucsra
ori myreg, (1 << mpcm)
andi myreg, ~( 1<<TXC )
out ucsra, myreg

This issue seems to have been fixed for mega169, where the data sheet clearly states that sbi and cbi might be used without problems.

--AVR Freak

admin's test signature
 

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Freaker--

I agree with your scenario, as far as I understand AVR internals. What I didn't think about is whether the setting of TXC would be "held off" when interrupts are disabled. But of course it can't be, because one can use TXC polled & not interrupt driven, so all interrupts could be off.

In any case [without testing], I can't see where this would be a problem in a half-duplex situation. Indeed, as in RS485 receiver enable, it would be processing the TXC for the last character of an outgoing message that would probably trigger setting the MPCM to watch for the next incoming.

For full-duplex operation, one would have to tread lightly but it could be done. In fact, wouldn't you set the MPCM immediately after receiving a message "for you", and before sending the response? No conflits then.

Lee

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

The message from noname points out what I missed. The TXC bit is 1 when set. Writting 1 to it clears the bit, thus the CLI, SBI problem. The correct solution involves clearing TXC in the word used to set or clear MPCM.

Thank you.

Also glad to hear that the 169, and presumably all newer chips have a hardware fix.

Laurence Boyd II