The datasheet, like usual, doesn't give nearly enough information about the DAC. If you set it to run in dual data mode (write two 16 bit values to DR0), which one does it sample first? There's only one actual DAC per set of channels, so one of them has to have higher priority and it's probably channel A, but I need to actually know what will happen and how long it will take to do both conversions back to back. Ideally they would happen at the exact same time, so I'm going to have to use DACIFB0 and DACIFB1 with the same event as the trigger, but it would be nice if it was possible to only use one DAC.
Does anyone know the specifics of how this works? You write a 32 bit value, an event triggers the conversions, and then what? Channel A then Channel B? How much time elapses between the first and second conversion? Etc.
From the datasheet:
Alternatively both samples to be converted can be written to DR0 in a single write cycle, in this
configuration the values for channel B and A are written to the upper and the lower half words of
DR0, respectively. This operation is possible only if the DAC Dual Data in Data Register A bit of
the Configuration register (CFR.DDA) is enabled.