In order to familiarize myself with the UC3 micros, I setup an ASF-based application, see below.
Purpose: toggle a single I/O pin as fast as possible.
Hardware: UC3A3256 Xplained board, I/O pin PB03, aka GPIO35.
The board has a 12 MHz Crystal connected to XIN0 / XOUT0; CPU clock is set up to be 6 MHz.
The disassembly also looks as expected:
We have a load-store sequence in an endless loop. The reference Manual on the UC3 tells me that the ld.w, mov, st.w and rjmp instructions all take one "issue latency" which I suppose to mean one machine cycle. So, we have seven instructions for one square wave at the pin.
At fCPU = 6 MHz, one instruction takes 166,7 ns, therefore one square wave on PB03 should take 166,7 * 7 = 1166,7 ns.
At least, this is what I expected to see.
My logic analyzer shows me this:
which is exactly half of the expected pin toggle frequency. The small deviation from 2,33333.... µs is due to the fact that the analyzer samples at 100 MHz / 10 ns intervals.
I then re-read the GPIO datasheet section 188.8.131.52 to find this:
I am not sure what this means - any access to GPIO over the Peripheral Bus always takes 2 instruction cycles ?
Any guidance appreciated.