UC3A UART Baud

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Trying a few things and cannot get my baud above 56700

I tried just the 12Mhz clock, and nothing, tried pll and can get it up to 54Mhz but still at 56700. I been playing with the PDCA thinking that would help and all I get garbage higher than that baud.

My project is to have 2 uarts. 1 is passing data back and forth, so that one needs a interrupt to handle incoming. The other one is more or less a debug uart to make sure its sending correctly. The debug works fine but at the baud listed above, nothing higher.

In the background, I am trying to do all kinds of checks.

So, I could use help with
1, Why no higher buad?
2. Can I run 240Mhz main clock with pll and the 12 Mhz for uarts?
3. Is PDCA the method I want.

Also tried to get the PDCA example to compile and I get 2 errors...from int.h

Severity and Description	Path	Resource	Location	Creation Time	Id
undefined reference to `ipr_val'	Project_2	intc.c	line 179	1200423488656	11180

ANy help be nice
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1a. The baud rate error grows to whopping 7% at 16x oversampling, 12MHz main clock and 115200 baud rate. Perhaps fractional part of the divisor would help you.
1b. PBA clock in the revision ES chips is limited to 33MHz.
1c. Sample of your code would help.

2. CPU clock is limited to 66MHz AFAIK.

3. PDCA not needed. I am running USART_1 in RS485 at 500 000 baud, interrupt based, without any problems so far. Previous post of mine has the source code as an attachment.

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OK thanks.

Can you explain more about the fractional divider?
I will post my code later as Its not here now.

Now, PBA is for uart i assume. Were does the PLL come in? I set PLL up, and it seems to run when switched to it. So am i not understanding correctly the way it works. I have it set to main clock and used 80 to 240Mhz. This is not the speed I am running at?

Also another crystal be in order?

Can you please post a link to your source..

Thanks for the reply. Going from 8 bit assembly to this is been a challange, and aside from things being buggy, I am happy with the new 32 bit platform. Just want to learn.

Mike

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Well I found your code, but it downloaded as php extension?

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Fractional baud rate means simply changing the divisor by a multiple of 1/8th. Formula and explanation are given in section "26.7.1.3 Fractional Baud Rate in Asynchronous Mode".

The source can also be found at: http://194.204.26.104/~andrei/av...

Perhaps you forgot to installation GCC header file fixes. This is described in UTILS/UTILS_Readme.html. It certainly would help to fix PDCA example.

As for the PLL, it is certainly a akin of a dark magic to me. I copied the code from DRIVERS/MACB/EXAMPLE/macb_example.c. By setting multipliers and dividers it was possible to produce core clock of 60 and 64 MHz, PBA clock half the frequency of core clock.

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I installed the GCC header fix.

As for the Pll, according to what I have read, I was able to set it to multiply by 19 and divide by 1. that should be 19+1 * 12Mhz should be 240Mhz. Than setting it to reflect the higher frequecy (not 80 to 120) and wait for lock and than switch over to the pll for main clock. I got all that working, but noticed it would lock up at that setting sometimes.

I got your example, so I will look that over. Still the whole clock thing is confusing. PBA?

I quess what I am looking for is the highest speed i can run code at and what i need to do to get the uart to function at my desired buad. I assume this can be done...

or is the pll just for certain things, like for usb clock ect.. I am pretty sure I did set it over to main clock.

I am at work and will post my code when I get home. Main thing is how to determine what needs to be set up for clocks to run 2 uarts at my choosing speeds. (Above 57600).

Thanks for your time.

Mike

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PBA is Peripherial Bus A and it is used by all the slow speed peripherials. I am sorry for writing too short messages. PBA speed limit is explained in the datasheet errata.

If this beetle ran at 240MHz it would be a record-breaking 4x overclocking. In case you didn't change the example, the PLL output is divided by 2 to get the core clock and once mor by 2 to get PBA clock. This gives core clock a more reasonable value of 120 MHz and PBA clock 60 MHz. Both are still over the legal limit.

By the way, if you had an access to oscilloscope, it can be used to verify baud rate by emitting series of 0x55 and measuring pulse width on the scope. Otherwise a simple periodic timer is also helpful since it runs on the very same PBA clock as the UART.

Hopefully this helps :)

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By the way, when receiving data stream at 500 000 baud, the processor executes approximately 1400 cycles between received characters. Beefy - yes :)

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Great thanks for the info. I did not get a chance to post my code last night as I will tongiht.

SO if i want i can run the core using the PLL at something reasonable and set the PBA to handle my uarts?

I think I understand. ALso I assume I could run another PLL at 43Mhz to handle usb stuff...?

Well than lets make this simple so I can grasp..

what would the settings be to do just that.

1. Run fast pll as main clock (thats stable)
2. run uarts at 115200 or higher (preferrably higher)

Could you post the setup for that?

I do have a scope, and will try that.

Again, I thanks you for your help. I am great with 8 bit avr's, and tried learning arm, and got frustrated and confused, and am giving this a shot, and so far I am pleased with everything. Just need to learn.

I gotta start another thread about using libriarys in avr32 as I can;t get em to work and don't want to hijack my own thread.

Thanks,

Mike

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Ok gonna try this myself as I don't want handouts, but to learn..

Quote:
volatile avr32_pm_t *pm = &AVR32_PM;

// Set PLL1 @ 48 MHz from Osc0.
pm_pll_setup(pm, 1, // pll.
9, // mul. so (9+1)* 12 = 120Mhz
1, // div.
0, // osc.
16); // lockcount.

//setup up PLL clock Options

void pm_pll_set_option(pm,
1, // unsigned int pll,
1, 0 = 160 to 240Mhz, 1 means 80 to 120Mhz
0, 0 means do not divide by 2, 1 does
1, enable wide band width)

// CLOCK STAYS AT 120MHz

if i did this:

void pm_pll_set_option(pm,
1, // unsigned int pll,
1, 0 = 160 to 240Mhz, 1 means 80 to 120Mhz
1, 0 means do not divide by 2, 1 does
1, enable wide band width)
Clock is 60Mhz

// Enable PLL1.
pm_pll_enable(pm, 1);

// Wait for PLL1 locked.
pm_wait_for_pll1_locked(pm);

// this switches ppl1 to main clock
void pm_switch_to_clock(pm,PPl1);

OK now I still confused about the PBA. Also whats up with the general clock? do I use PBA or General for the uarts?

I am getting there.

Mike

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ok timers and stuff used general clock

PBA will be for perif's like uart

So if i want 2 different uart bauds I need PBA for usart 0 and PBB for usart 1.

Let me see what I can dig up on setting those up.

Mike

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//FIXME update this header -SM
/*!
* \brief This function will select all the power manager clocks.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param pbadiv Peripheral Bus A clock divisor enable
* \param pbasel Peripheral Bus A select
* \param pbbdiv Peripheral Bus B clock divisor enable
* \param pbbsel Peripheral Bus B select
* \param hsbdiv High Speed Bus clock divisor enable (CPU clock = HSB clock)
* \param hsbsel High Speed Bus select (CPU clock = HSB clock )
*/
extern void pm_cksel(volatile avr32_pm_t *pm, unsigned int pbadiv, unsigned int pbasel, unsigned int pbbdiv, unsigned int pbbsel, unsigned int hsbdiv, unsigned int hsbsel);

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ok now back to the uart problem
I got your code, but i want asyn rs232 mode
I am looking at this fractional baudt rate.
Is this where I need to foucs?

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What baud rate do you need?

For example, 115200 should work very fine (error is 0.2% only) with 48 MHz core clock and 24 MHz PBA clock.

Thus, it is sufficient to copy the PLL setup from the example without any changes. Don't forget to change the clock frequency macros (FPBA?) to the correct values.

The AVR32UC3A block diagram (page 5 in the datasheet) shows all USART-s connected on PBA. PBB is connected to high-speed devices.

P.S. my fractional part code in IUcart.c has probably a bug.

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Thats what I am lacking is the FPBA stuff

I don't see how to set it. I think I fully understand setting the PLL. No problem there.

But than I think I use...pm_cksel but i see that I can only enable the divide enable. I assume it 2.

So with that

I would expect

pm_cksel pm,
1,
1,
0,
0,
0,
0

SO how do i tell it to use PPL1 that I just set up?

were are the clock frequency macros.. lost here

I am close to understanding

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Also I see I can maybe use this for the uart too..
its in the usart.c code

usart_set_baudrate(xxxx)

BTW thanks alot for you time and help. :D

Also lets just try a 115200 baud for now, and once I see how to make that happen I will try for higher on my own.

Mike

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ohh heck, do I need to enable the moudle for each uart???

// Assign GPIO to USART.
gpio_enable_module(USART_GPIO_MAP,
sizeof(USART_GPIO_MAP) / sizeof(USART_GPIO_MAP[0]));

If this for Uart 0?

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#if BOARD == EVK1100
# define DBG_USART (&AVR32_USART1)
# define DBG_USART_RX_PIN AVR32_USART1_RXD_0_PIN
# define DBG_USART_RX_FUNCTION AVR32_USART1_RXD_0_FUNCTION
# define DBG_USART_TX_PIN AVR32_USART1_TXD_0_PIN
# define DBG_USART_TX_FUNCTION AVR32_USART1_TXD_0_FUNCTION
# define DBG_USART_BAUDRATE 57600

static const gpio_map_t DBG_USART_GPIO_MAP =
{
{DBG_USART_RX_PIN, DBG_USART_RX_FUNCTION},
{DBG_USART_TX_PIN, DBG_USART_TX_FUNCTION}
};

// Setup GPIO for debug USART.
gpio_enable_module(DBG_USART_GPIO_MAP,
sizeof(DBG_USART_GPIO_MAP) / sizeof(DBG_USART_GPIO_MAP[0]));

this sets usart 1 so if i change (&AVR32_USART1) to (&AVR32_USART0) and send the same code would that map things for usart 0?

Mike

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soo close to grasping all this

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ok if I am learning right:

I can do this
// Set PLL1 @ 48 MHz from Osc0.
pm_pll_setup(pm, 1, // pll.
3, // mul.
1, // div.
0, // osc.
16); // lockcount.

// Enable PLL1.
pm_pll_enable(pm, 1);

// Wait for PLL1 locked.
pm_wait_for_pll1_locked(pm);

// Setup USB GCLK.
pm_gc_setup(pm, AVR32_PM_GCLK_USB, // gc.
1, // osc_or_pll: use Osc (if 0) or PLL (if 1).
1, // pll_osc: select Osc0/PLL0 or Osc1/PLL1.
0, // diven.
0); // div.

// Enable USB GCLK.
pm_gc_enable(pm, AVR32_PM_GCLK_USB);

which setups up my usb gc and i CAN STILL USE PLL1 to set the PBA to 24MHz?

Also with this, my main clock is still at the 12Mhz xtal becuase I never set it or is it now my main clock is the gc set to 48Mhz...?

PLL1 is set to 48Mhz but can't be used for USB, which needs the General clock??

Is my madness correct?

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Hey, you are welcome :)

Yes, the 0->1 change would make it work with USART_0. I am not sure why the GPIO has to be setup externally to the usart library -- it seems that it is most flexible way. In case you haven't noticed: there are several set of pins on which to map USART_0 signals. The alternative pins, however, coincide with the SDRAM pins, thus they cannot be used at the same time.

The EVK1100 board has bugs in the RS232 control signals, see last page in the file EVK1100_SCHEMATICS_REVC.pdf for details. That's probably why all of the examples use USART_1.

I am not sure about how to change the frequency macros for the example projects. I have copied (and heavily modified) the relevent source files in my project.

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I am sorry, I am not familiar with USB peripherials (yet).

I suggest starting with the example in the directory "DRIVERS/PM/EXAMPLE2/". This is known to set CPU clock at 48 MHz and PBA clock to 24 MHz; which theoretically should enable working with USART at 115 200 baud.

Perhaps it helps to disable 8x oversampling and set up USART only in 16x oversampling mode. The relevant code is in DRIVERS/USART/usart.c. It certainly helped me, but I might have made a real mistake elsewhere.

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OK, sounds good. I got enought read time and once I get out of work, I am gonna go home and test in real life if I can get this to work.

This chip and platform by far has made alot of things so much clearer that I did not understand on the arm chips.

Also you help, has made things much understandable.

I will have a slew of questions about how to's as my code progresses.

Thanks again for your time

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SOLVED

Seems I been a victum of Atmel

What happened was i have my baud setting in a .h file and call a debug print function. Well it appears if I modify the .h and do a save all, it stays the same unless I modify the .c file that matches that .h file.

I know avr32 studios is buggy as hell, but never thought that one.

heres my working code

volatile avr32_pm_t *pm = &AVR32_PM;
	
  // switch to oscillator 0
  pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP);

  // Set PLL0 @ 48 MHz from Osc0.
  pm_pll_setup(pm, 0,   // pll.
                   7,   // mul. This Plus 1 times xtal = Speed
                   1,   // div.
                   0,   // osc.
                   16); // lockcount.
                   
  pm_pll_set_option(pm, 0,  // pll
  	                    1,  // 0 = 160-240Mhz. 1 = 80-180Mhz
						1,  // Divide Output Freq by 2
						0); // Wide-Bandith Mode Enabled
   
  // Enable PLL0.
  pm_pll_enable(pm, 0);

  // Wait for PLL0 locked.
  pm_wait_for_pll0_locked(pm);
  
   /* Divide PBA clock by 2 from main clock (PBA clock = 48MHz/2 = 24MHz).
     Pheripheral Bus A clock divisor enable = 1
     Pheripheral Bus A select = 0
     Pheripheral Bus B clock divisor enable = 0
     Pheripheral Bus B select = 0
     High Speed Bus clock divisor enable = 0
     High Speed Bus select = 0
  */
  pm_cksel(pm, 1, 0, 0, 0, 0, 0);
  
  // Set one wait-state (WS) for flash controller. 0 WS access is up to 30MHz for HSB/CPU clock.
  // As we want to have 48MHz on HSB/CPU clock, we need to set 1 WS on flash controller.flashc_set_wait_state(1);
  flashc_set_wait_state(1);
  
  // Main Clock Connected to PLL0
  pm_switch_to_clock(pm,AVR32_PM_MCSEL_PLL0);   
  
  // init debug serial line
  init_dbg_rs232(24000000);
  

the init_dbg_rs232 is in my print debug c code and it calls this:

void init_dbg_rs232(long pba_hz)
{
  static const gpio_map_t DBG_USART_GPIO_MAP =
  {
    {DBG_USART_RX_PIN, DBG_USART_RX_FUNCTION},
    {DBG_USART_TX_PIN, DBG_USART_TX_FUNCTION}
  };

  // Options for debug USART.
  static const usart_options_t DBG_USART_OPTIONS =
  {
    .baudrate = DBG_USART_BAUDRATE,
    .charlength = 8,
    .paritytype = USART_NO_PARITY,
    .stopbits = USART_1_STOPBIT,
    .channelmode = USART_NORMAL_CHMODE
  };

  // Setup GPIO for debug USART.
  gpio_enable_module(DBG_USART_GPIO_MAP,
                     sizeof(DBG_USART_GPIO_MAP) / sizeof(DBG_USART_GPIO_MAP[0]));

  // Initialize it in RS232 mode.
  usart_init_rs232(DBG_USART, &DBG_USART_OPTIONS, pba_hz);
  
 // usart_set_baudrate(DBG_USART,256000,24000000);
}

notice the remmed out baudrate line at the end? I tried that and it did not compile so i remmed it and than my changes in the same . h file took and compiled right

Here is the matching .h settup:

#if BOARD == EVK1100
#  define DBG_USART               (&AVR32_USART1)
#  define DBG_USART_RX_PIN        AVR32_USART1_RXD_0_PIN
#  define DBG_USART_RX_FUNCTION   AVR32_USART1_RXD_0_FUNCTION
#  define DBG_USART_TX_PIN        AVR32_USART1_TXD_0_PIN
#  define DBG_USART_TX_FUNCTION   AVR32_USART1_TXD_0_FUNCTION
#  define DBG_USART_BAUDRATE      128000

#elif BOARD == EVK1101
#  define DBG_USART               (&AVR32_USART1)
#  define DBG_USART_RX_PIN        AVR32_USART1_RXD_0_0_PIN
#  define DBG_USART_RX_FUNCTION   AVR32_USART1_RXD_0_0_FUNCTION
#  define DBG_USART_TX_PIN        AVR32_USART1_TXD_0_0_PIN
#  define DBG_USART_TX_FUNCTION   AVR32_USART1_TXD_0_0_FUNCTION
#  define DBG_USART_BAUDRATE      115200
#endif

thats were I been changing my baud rate.

SOOOO.... Damn ATMEL got me again.

Hey bro, thanks for all your help, but now I can start a new thread with my next problem.

As a Result I think I understand the clock and powermangement and Uart framework very well now.

HAPPY MAN

Mikey

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ok so now i can't go 256000 baud but below that works. Seems I can play a bit more.

Can A mod put SOLVED in title and maybe this can help others.

AVR32 studios will not accept any h file change in frameworks unless you do something to the related .c file.

Mike

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well it accepts it and shows changes but does not compile it...

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one last question

/* Divide PBA clock by 2 from main clock (PBA clock = 48MHz/2 = 24MHz).
Pheripheral Bus A clock divisor enable = 1
Pheripheral Bus A select = 0
Pheripheral Bus B clock divisor enable = 0
Pheripheral Bus B select = 0
High Speed Bus clock divisor enable = 0
High Speed Bus select = 0
*/
pm_cksel(pm, 1, 0, 0, 0, 0, 0);

why are we not setting Pheripheral Bus A select = 0

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Good to hear that it works :)

The pm_cksel options are explained in the AT32UC3A datasheet, page 67. Namely, if PBADIV==1, the clock is divided by 2^(PBASEL+).

By the way, it looks like the example programs in the framework are fine by itselves. However, as soon as one starts combining examples, all kind of issues will turn up. Right at the very same moment I am working on getting SD/MMC and LCD display to work simultaneously.

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Ok i can get 128000000 buad but nothing higher

I want to hit lets say 256000 which is the highest default in brye terminal.

I figured with usart clock at 24Mhz this should be no problem as to only changing my buad.

But I get garbage...

Mike

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ok not making since
I made a excell sheet where I can enter in buad i want and the clock speed and it figures error on usart

for 115200 i get:

Clock	Baud	Calc. CD	CD	Actual	Error
24000000	115200	13.02083333	14	107142.8571	7.52

which yields a 7.52 error which explains why somethings I get missed characters.

Now i try with 256000 the highest in brye term and i get:

Clock	Baud	Calc. CD	CD	Actual	Error
24000000	256000	5.859375	6	250000	2.4

Nice 2.4 percent error, but yet I see nothing but garbage on the brye terminal.

I'll upload my excell sheet..

Mike

Attachment(s): 

Last Edited: Mon. Jan 21, 2008 - 10:04 PM
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less error I would expect to see this. Also not sure if it matters but i am using usb convertor....

Mike

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BTW A2 and B2 are were you enter your desired data.

The rest gets calculated...

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ok with that small error fixed
still 2.something error should work?
they say anything over 5% is no good

Clock	Baud	Calc. CD	CD	Actual	Error
24000000	115200	13.02083333	13	115384.6154	-0.16
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well the best error I can get for a 256000 baud is this:

Clock	Baud Rate  Calculated CD	CD	 Actual Baud Rate	Error
33000000	256000	8.056640625	8	257812.5	-0.703030303

I will test this tonight when I get home and see what my ouput looks like.

The avr 8 bit usarts are so much easier to get higher bauds than this beast.

This is pushing the 33Mhz limit on the PBA....

Mike

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well no go at 256000 all garbage. Also at 66Mhz in PLL mode I locked up.....

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Comparison of different PBA clocks:

Clock	Baud Rate	Calculated CD	CD	 Actual Baud Rate	Error
4000000	1152000	0.217013889	0	#DIV/0!	#DIV/0!
4000000	256000	0.9765625	1	250000	2.4
8000000	115200	4.340277778	4	125000	-7.84
8000000	256000	1.953125	2	250000	2.4
10000000	1152000	0.542534722	1	625000	84.32
10000000	256000	2.44140625	2	312500	-18.08
12000000	115200	6.510416667	7	107142.8571	7.52
12000000	256000	2.9296875	3	250000	2.4
14000000	1152000	0.759548611	1	875000	31.65714286
14000000	256000	3.41796875	3	291666.6667	-12.22857143
16000000	115200	8.680555556	9	111111.1111	3.68
16000000	256000	3.90625	4	250000	2.4
18000000	1152000	0.9765625	1	1125000	2.4
18000000	256000	4.39453125	4	281250	-8.977777778
20000000	115200	10.85069444	11	113636.3636	1.376
20000000	256000	4.8828125	5	250000	2.4
22000000	115200	11.93576389	12	114583.3333	0.538181818
22000000	256000	5.37109375	5	275000	-6.909090909
24000000	115200	13.02083333	13	115384.6154	-0.16
24000000	256000	5.859375	6	250000	2.4
26000000	1152000	1.410590278	1	1625000	-29.10769231
26000000	256000	6.34765625	6	270833.3333	-5.476923077
28000000	115200	15.19097222	15	116666.6667	-1.257142857
28000000	256000	6.8359375	7	250000	2.4
30000000	115200	16.27604167	16	117187.5	-1.696
30000000	256000	7.32421875	7	267857.1429	-4.426666667
32000000	115200	17.36111111	17	117647.0588	-2.08
32000000	256000	7.8125	8	250000	2.4
33000000	1152000	1.790364583	2	1031250	11.70909091
33000000	256000	8.056640625	8	257812.5	-0.703030303

I quess what I should try is my 256000 at the acutal baud rate and see what the output looks like...

I did verify my CD is being set at 8 so either 1 of 2 things is happening.

1. my usb to serial converter is not happy with that speed.

2. Atmel Usart has some issues not talked about yet.

Also still bothers me that I should be able to run the core cpu clock at 66Mhz to give me that 33Mhz PBA but I know i can't as I lock up and stall out.

Mike

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sorry the chart does not present itself right, and I noticed the download was same thing I seen before here, downloads as php file.

ANyways the forumla I used is:

Calculated CD = clock/(Baud * 16)

Actual CD is rounded

Actual baud = clock/(CD*16)

error = (buad/acutal baud) - 1 * 100

So I know it tries to get as close as it can, but maybe at that high of speeds, I should set my terminal with a custom value of actual calculated baud and see what happens.

I hope this helps somebody else struggling with this uart....

Last Edited: Tue. Jan 22, 2008 - 04:03 PM
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Assuming OVER is set to 1

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without my project being able to handle above 12800 buad, world wide takeover will not be possible.

Mike

Last Edited: Tue. Jan 22, 2008 - 04:02 PM
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Also can anyone explain what a - error means?

I know 0 is is perfect and plus it goes bad so when they show a - (negative) error, wth does that mean?

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Hi, Mike,

mikedong wrote:
ok with that small error fixed
still 2.something error should work?
they say anything over 5% is no good

The AVR 8-bit series datasheets cover USART baud rate settings very throughly. There is a table in the ATmega88 datasheet listing allowed baudrate error vs. number of data bits + parity bit. For 8 data bits and 1 parity bit the recommended error is 1.5%.

It might be that the usb-serial converter is at fault. I have heard that FTDI based ones are better at non-traditional baud rates than Prolific chips; however, I can not confirm this rumour. Measurement of the real baud rate of this usb-serial converter will clarify this point.

As for the 24 MHz PBA clock and 256 000 baud rate, your calculated error is correct. Perhaps fractional baud rate comes to help -- with CD=5, FP=7 the error is 0.3% and thus in the allowed range.

Hopefully this helps :)

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ok great, but i notice when the baud is set using framworks usart.h, nothing about FP is mentioned or manuipulated.

I am now assuming i will need to adapt my own code for that?

Great, thanks for you time and reply.

Mike

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Yes. I suggest first hardcode the CD and FP values into the code before doing automatic calculation.

My code in the IUsart.zip calculates best FP on its own :)

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got yah.

Doing my homework I come up with...

usart->brgr = (0x05 << AVR32_USART_BRGR_CD_OFFSET) | (0x07 << AVR32_USART_BRGR_FP_OFFSET);

Gonna try this tonight, and also i will try 2 usb convertors connected together and test for highest baud to rule them out.

Life is good.

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Well done :)

Btw, when you have two identical ones (they can be identified by the drivers), they will err in exactly the same way...

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great.

But if I bypass set_baud I need to ensure my OVER is set to 16x which I think is 0, but to be safe I would include this as well:

usart->mr &=~ AVR32_USART_MR_OVER_MASK;

Not to shabby for 2 weeks in 32 bit world and new to C coding.

Mike

[/code:1][code:1]
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well here is my calculated error

Quote:
24000000 256000 5.859375 5 300000 -14.66666667 0 7 255319.1489 0.266666667

the last baud shows with FB and is .2666667 which is good. Also It shows me that is at my 24Mhz clock which means I can set PLL back to 48, as it runs good at that speed. Untill I can figure out why I lock up 66Mhz cpu clock, this is the best I think I can get it.

So, only 2 things left

1. USB convertors again, which I will easly test tonight (Yes I have matching ones.)

2. Atmel has forgot to mention higher Bauds don't work on this chip.

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And have learned all about setting up 232 usarts.

This was the real reason for all this to begin with.

I really don't need that high of a speed for my project. I just wanted to become able to set up this chips usart as I please.

Thanks for all those you helped.

Mike

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well no go, still garabage.

Need to test the usb to serial convertors.

Mike

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It certainly has been a long way to master these pesky USART-s :)

At this point, a scope would really help.

How do you test for baud rate mismatch when you have identical usb-serial converters? Think :)

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I run 2 instances of hyper terminal running.

I plug in each usb convertor and set em to the appropriate port, and same configure.

than taking a cable inbetween em I type anything in 1 window, and it should appear in the opposite window.

I think its a null cable I used. Now sure but rx goes to tx and visa versa ....

I am gonna try to get that tested today...

Mike

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