UC3 DAC offset calibration does not work correct

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Hi Freaks,

i've found that the DACIFB offset calibration register OCR does not work correct for UC3(C).

While working on the DAC calibration function i found out that i was not able to get a DAC output lower than approx. 40mV (reference 3,3V VDDANA).
I then tried to set different offset calibration values by hand and found this:
- OCR values lower between -209 and 0 increase the offset.
- OCR values below -209 or above 0 do not change anything, offset doesn't get smaller.
So i guess the data format is not really 9bit with sign as described in the datasheet but 8 bit with an additional sign bit as 9th bit. This is a bit irritating but i can live with it.
Whatever i tried i found no way to get the offset below 40mV since configuring positive values (i've tested the full range between 0 and 0xFF) do not change the offset. So the offset mechanism looks broken in one direction.

Has anyone worked with the UC3 DAC and want's to share the experience?
Did yu manage to calibrate the offset and how?

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I found both the ADC and DAC in the UC3C to be quite poor, I would never use them again. But given they are needed by the current hardware I had to make due. For the ADC I kept the "factory calibration" for the gain since I had no other source I could use. I configured it to tie it's internal inputs together to measure offset and did an iterative operation to get it set correctly.

For the DAC I was fortunate in that I only needed an output range of 1.0 to 2.0 Volts to set the current limit for some stepper motor driver chips. After trying to get the DAC calibration register to do something useful I gave up and just calculated offset and gain values (using the ADC to measure the DAC output) and used those when writing to the DAC output register. Not terribly accurate but it was good enough for my purposes.

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Thanks for this info. It's basically what i find as well.

Regarding the ADC offset calibration i used the newest ASF 3.8.1 function and it seems to work so far. It measures the internal ground. The result is at least not way off.

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In most designs I try to keep all my analog signals at least 0.6V away from the supply rails. This way, I don't need "rail-to-rail" OP amps and the issues they have. It also gives me more confidence in the AD samples I read, as there are headroom either way.
In your case, I suspect the DAC is facing some problems very close to the negative rail (0V).