On a UC3A0512 rev.I, I have one ADC channel enabled, conversion is triggered by a timer channel, and PDCA is taking the data away. This basically works.
What I ran into is this in the datasheet:
Converting a single analog value to a 10-bit digital data requires Sample and Hold Clock cycles as defined in the field SHTIM of the MR register and 10 ADC Clock cycles. The ADC Clock frequency is selected in the PRESCAL field of the MR register.
For performance and electrical characteristics of the ADC, see the DC Characteristics section.
So what does that hint at?
384(1) kSPS Throughput Rate ADC Clock = 5 MHz
1. Corresponds to 13 clock cycles at 5 MHz: 3 clock cycles for track and hold acquisition time and 10 clock cycles for conversion.
With SHTIM=2 (3 cycle t/h), matching the stated 5MHz/384kps=13 adclock/sample throughput, I got the impression that I could do 384ksps throughput.
In reality, the ADC does not seem to accept triggers faster than 15 adclock, leading to a maximum single channel througput of 333kHz.
Has anyone else run into this, and/or this documented anywhere?