Bit 7 – RXCIF USART Receive Complete Interrupt Flag
This flag is set when there are unread data in the receive buffer and cleared when the receive buffer is empty.
OK. I thought I understood RXC/RXCIF, but now I'm not sure. I've reviewed old posts, and they're not really helping a lot.
I want, like many others, to implement rs485 (for Optiboot, as it happens), on mega0/xTiny. That means waiting until for both the TX shift register and the TX data register to be empty before disabling the "transmiter" external circuit. In my case, in a polled environment. This is the realm of the TXC flags, which shows up as TXCIF in USART.STATUS on the xmega-like chips. It's "well known" to be problematic, with inconvenient "automatic clearing" when the ISR is serviced, and inconvenient not-clearing unless you actually use the interrupts.
I THOUGHT that the main problem was the "not-clearing" part, and by clearing the flag manually (by writing a 1) you'd be able to tell when transmissions were complete.
But apparently, if you clear TXCIF while no output is in progress (both shift register and data register are empty), it will simply STAY cleared until you actually send at least one character.
I think this means that there is no way to check whether the transmitter is idle form an "ignorant" piece of code (that doesn't know whether there has been a recent transmit or not.) Is that true? (I want to turn off the transmitter in my "getch()" function, since stk500v1 is nicely lock-step, and won't be trying to receive commands unless it's done transmitting. But it doesn't transmit anything at startup...)
(Yes, I realize the the xmega USART has an rs485 mode that will set a particular pin appropriately. I was hoping for more freedom of choice in pin selection. If I had "internal" access to the state of that XDIR bit, that would solve all my problems. But that doesn't seem possible, either.)