I'm trying to understand part of the TWI specification in the AT90CAN128 data sheet. The other AVR data sheets I have looked at have the same timing requirements.
Tlow Low Period of the SCL Clock:
Fscl < or = to 100 kHz (6) 4.7 us minimum
6. The actual low period generated by the AT90CAN32/64/128 Two-wire Serial Interface is (1/Fscl - 2/Fck), thus fCK must be greater than 6 MHz for the low time requirement to be strictly met at Fscl = 100 kHz.
Fscl > 100 kHz (7) 1.3 us
7. The actual low period generated by the AT90CAN32/64/128 Two-wire Serial Interface is (1/Fscl - 2/Fck), thus the low time requirement will not be strictly met for Fscl > 308 kHz when Fck = 8 MHz. Still, AT90CAN32/64/128 devices connected to the bus may communicate at full speed (400 kHz) with other AT90CAN32/64/128 devices, as well as any other device with a proper Tlow acceptance margin.
I'm having trouble getting the math behind the conclusions about Fck speed requirements. Just using (1/Fscl - 2/Fck) with Fscl = 100 KHz and Fck = 4 Mhz I get a result of 9.5 us. If I use Fck = 8 Mhz I get 9.75 us. I cannot see how 9.5 us or 9.75 us relates to 4.7 us minimum at 6 MHz Fck. I would have expected to see some timing boundary crossed between the 6 MHz specified as the minimum clock speed. Maybe I'm just missing something easy to see. I would appreciate any help explaining this.