TWI timing specification in the data sheets - answered

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I'm trying to understand part of the TWI specification in the AT90CAN128 data sheet. The other AVR data sheets I have looked at have the same timing requirements.

AT90CAN128 data sheet wrote:
Tlow Low Period of the SCL Clock:

Fscl < or = to 100 kHz (6) 4.7 us minimum

6. The actual low period generated by the AT90CAN32/64/128 Two-wire Serial Interface is (1/Fscl - 2/Fck), thus fCK must be greater than 6 MHz for the low time requirement to be strictly met at Fscl = 100 kHz.

Fscl > 100 kHz (7) 1.3 us

7. The actual low period generated by the AT90CAN32/64/128 Two-wire Serial Interface is (1/Fscl - 2/Fck), thus the low time requirement will not be strictly met for Fscl > 308 kHz when Fck = 8 MHz. Still, AT90CAN32/64/128 devices connected to the bus may communicate at full speed (400 kHz) with other AT90CAN32/64/128 devices, as well as any other device with a proper Tlow acceptance margin.

I'm having trouble getting the math behind the conclusions about Fck speed requirements. Just using (1/Fscl - 2/Fck) with Fscl = 100 KHz and Fck = 4 Mhz I get a result of 9.5 us. If I use Fck = 8 Mhz I get 9.75 us. I cannot see how 9.5 us or 9.75 us relates to 4.7 us minimum at 6 MHz Fck. I would have expected to see some timing boundary crossed between the 6 MHz specified as the minimum clock speed. Maybe I'm just missing something easy to see. I would appreciate any help explaining this.

Last Edited: Sat. Dec 9, 2006 - 04:20 AM
Total votes: 0

Mike,

Just at a guess, I'd say the datasheets have a typo in them (including my '128 sheet). I think the wording should be:

the actual low period .... is (1/2Fscl -2/Fck)

i.e. just a little short of half the full-cycle period. Then the other numbers start to make sense. e.g. 2/6MHz == 0.3(333) usec, so that the low period becomes 5 - 0.3 = 4.7 usec. Similarly for the other statements, allowing for the inevitable rounded values.

Roger

Total votes: 0

I just got this back from ATMEL:

ATMEL support wrote:
The expression should be (1/2*Fscl-2/Fck)

Fck=6 MHz gives 4.67uS
Fck=7 MHz gives 4.71uS
So the idea was that Fck needed to be higher than 6MHz (or close to 7MHz) to meet these requirements.

The answer was in regard to note 6. It looks like lots of data sheets have a TWI formula typo (at least all the data sheets I have found). Given that the published formula was way wrong, has anyone ever bothered to check their TWI setup timing parameters :? ?

Roger got it right, except that rounding the result is not part of the answer. Interpreting the data sheet is not quite as literal as I thought it was (at least in a strict mathematical sense).