I have a project with 2 ATMega48 both configured as TWI master and slave. I noticed that after a couple hours, the TWI modules stop working and I have to reset the AVR's in order to resume operation.
I cleaned up my application to the bare minimum in order to test this issue and increased the communication rate on the bus. I now can crash the modules in seconds. Both AVR have the same program loaded except the slave and target addresses are swapped. There's a random delay before issuing a start condition so that both have equal chances to be master.
After analysis, it seems to me that there's a bug in the TWI hardware module when both masters are configured simultaneously to send a start. (TWSTA set in TWCR)
The program can run for a couple of seconds, during this period both AVR's are master/slave by turns. Most of the time both set TWSTA around the same time but because one is slightly before the other, one becomes master and the second slave.
From repetitive measurements, I could determine that the condition to crash the bus is that both TWSTA are set within approximately 5µs. Then 2 glitches appear after the stop condition and seems to crash the TWI module because the bus freezes from that point.
I also monitored TWSR during all communications and everything is normal there.
I attached a more detailed report of this problem with screenshots of the signals. There's also the test code I used in the rar file.
Has anybody else experienced this too? I've seen on different posts that people had problems in this mode but without good analysis of the problem. Maybe this is related.
I'd like to have your opinion before I contact Atmel.