TWI between atMega328P (master) and atTiny85 (slave)

Log in or register to post comments
Go To Last Post
9 posts / 0 new
Author
Message
gregd99
gregd99's picture
Level: Resident
Joined: Mon. Oct 10, 2011
Posts: 667 View posts
Location: Sydney, Australia
#1
Posted by gregd99: Sat. Apr 9, 2022 - 02:28 PM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I have implemented master and slave code based on the AVR application notes and can happily transmit multiples bytes of data in MTX mode. (hooray)

 

However in MRX mode, at the end of the sequence (SLA+R, 3 data bytes), I get an 0x38 status - loss of arbitration - with SCL high and SDA low. I am not sure if the line levels are the cause of the problem.... I suspect the consequence of whatever is going wrong. Having wrestled with the setup for a while, I found and tried Don Blake's code (Thanks Don). Although based (I think) on the ANs the implementation is pretty different. However.... I get the same 0x38 status code.

 

Without asking someone to dig through the code... has anyone had this sort of issue?

With the same issue in two sets of code... it seems to say it is something about my setup.

I have 4k7 pull-ups fitted and the issue seems to be invariant with clock rate.

 

Any ideas gratefully accepted!

 

Thanks

Greg

regards
Greg

Tags:

AVR Microcontrollers, megaAVR and tinyAVR
Last Edited: Sat. Apr 9, 2022 - 03:04 PM
Top
Bronze Markdavid.prentice
david.prentice's picture
Level: 10k+ Postman
Joined: Sat. Feb 12, 2005
Posts: 31913 View posts
Location: Wormshill, England
Posted by david.prentice: Sat. Apr 9, 2022 - 03:04 PM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Are you taking the p*ss ?

 

The Tiny5 has only got 512 bytes of Flash and no USI.

 

However the Tiny20 and Tiny40 from the same brain-dead Tiny family have more Flash, SRAM and dedicated TWS hardware.

TWI Slave using TWS peripheral works far better than USI.   And in my opinion better than the Mega's TWI in Slave mode.

 

In simple terms.   USI, TWS, TWI peripherals from traditional AVR work fine as a Slave.   TWIx works fine on Xmega.  TWI0 works fine on Mega4809, AVR128DA, AVR128DB, ...

 

David. 

Last Edited: Sat. Apr 9, 2022 - 03:08 PM
Top
gregd99
gregd99's picture
Level: Resident
Joined: Mon. Oct 10, 2011
Posts: 667 View posts
Location: Sydney, Australia
Posted by gregd99: Sat. Apr 9, 2022 - 03:06 PM (Reply to #2)
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Well it would’ve been… Except it with the typing mistake. I corrected the title to 85. Apologies

regards
Greg

Top
Bronze Markdavid.prentice
david.prentice's picture
Level: 10k+ Postman
Joined: Sat. Feb 12, 2005
Posts: 31913 View posts
Location: Wormshill, England
Posted by david.prentice: Sat. Apr 9, 2022 - 03:16 PM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

No problem.   Tiny85 or any AVR with USI works fine as a Slave.

 

For years I was pleased with the Don Blake mod.

However I prefer a slightly different logic.

 

If you describe how you want your Slave to work,  I will implement the behaviour.   And write a suitable test-suite.

 

If you are unsure how to describe it,  just quote the part number of a real-life hardware chip that is similar.

Then I have a real-life datasheet to follow.

 

David.

Top
gregd99
gregd99's picture
Level: Resident
Joined: Mon. Oct 10, 2011
Posts: 667 View posts
Location: Sydney, Australia
Posted by gregd99: Sat. Apr 9, 2022 - 03:26 PM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

David,

That is very generous offer. Thanks so much.

 

I’m looking for pretty generic behaviour from the slave. I want to be able to

1) receive three bytes of data plus the address byte in MTX mode and

2) respond with three bytes of data in MRX mode. 

restarts would be nice but the focus is on getting the basics going. 
 

The code I have written does this the above but I have the problem with loss of arbitration. I am wondering if it is something physical and was hoping the collective history on this forum might result in someone saying “I remember…“

 

if you have something tested that does something similar it would be much appreciated. 
 

thanks very much

 

 Greg
 

 

regards
Greg

Top
Bronze Markdavid.prentice
david.prentice's picture
Level: 10k+ Postman
Joined: Sat. Feb 12, 2005
Posts: 31913 View posts
Location: Wormshill, England
Posted by david.prentice: Sat. Apr 9, 2022 - 03:46 PM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Look at the DS13007 datasheet.   Registers 8 .. 63 just store regular SRAM.

 

e.g. write "David" starting at address 23.   i.e. stored at 23 - 27

 

<S> <0xD0> <23> <'D'> <'a'> <'v'> <'i'> <'d'> <P>

 

And you can read by

 

<S> <0xD0> <23> <S> <0xD1> <'D'> <'a'> <'v'> <'i'> <'d'> <P>

 

Note that DS1307 has Slave address 0xD0 for Write,  0xD1 for Read.

 

I suggest that you use a regular library for the Master.  e.g. i2c_master.h or Wire.h

 

Your Tiny85 has got 512 bytes of SRAM.   So you could easily store 256 bytes of Slave "memory".  e.g. registers 0 .. 255

 

David.

Top
gregd99
gregd99's picture
Level: Resident
Joined: Mon. Oct 10, 2011
Posts: 667 View posts
Location: Sydney, Australia
Posted by gregd99: Tue. Apr 12, 2022 - 11:35 AM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Thanks for your helpful suggestions.

 

The issue turned out to be that I was trying to read from the slave when it had no data in its tx queue. The response from the slave was (I think) to hold the data line low and this was reported as loss of arbitration. I have note read through the IIC spec to check if the is "correct" but at least it is plausible.

 

An atmega328p happily communicates with an atTiny85 with a 400kHz clock, 4k7 pull-ups and random 5 cm jumpers connecting the boards together (plus a ground jumper). :-)

 

I am using interrupt driven master and slave.... but the Don Blake polled code for the master end is a nice, simple implementation that was helpful in diagnosing my issues.

 

Regards

Greg

regards
Greg

Top
ki0bk
ki0bk's picture
Level: 10k+ Postman
Joined: Mon. Sep 8, 2014
Posts: 10649 View posts
Location: Over the rainbow
Posted by ki0bk: Tue. Apr 12, 2022 - 12:34 PM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

the protocol usually has the master send a nak to the final byte received from the slave, so the slave knows to release the bus to the master so it can send stop!

Does you master do that?

 

Jim

 

 

FF = PI > S.E.T

 

Top
gregd99
gregd99's picture
Level: Resident
Joined: Mon. Oct 10, 2011
Posts: 667 View posts
Location: Sydney, Australia
Posted by gregd99: Tue. Apr 19, 2022 - 12:09 PM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I thought I had replied to this message....

 

Thanks for the suggestions and hints.

The issue I had was that I was (accidentally) sending a repeated start. The issue was my application layer rather than the TWI operation.

 

Thanks

Greg

regards
Greg

Top