I've been working on some fairly complete AVR CPU instruction and timing tests. They're mainly to be sure that simavr's CPU simulator is accurate (after some fixes it passes these). They'd be useful for someone writing a simulator or making their own AVR-compatible core.
The instruction test runs each instruction with all registers set to various values,
then checksums values in registers and on stack, and compares with table of
correct checksums. Many combinations of values are set up for each
instruction, triggering edge cases and various status flag outputs. So it's
purely pass/fail. Lots of testing bang-for-the-coding buck. It'll catch an
instruction modifying the wrong register, changing the stack, etc. Failures
list the address in the .lss file where you can see what instruction
failed. I've used a similar structure successfully in many testers: 6502,
GB-Z80, SPC-700. It's based on zexall's approach for testing the Z80 CPU.
The timing test runs each instruction while a timer is counting. It times branches both ways, so taken/not taken times are tested.
Both "calibrate" by simply running it on hardware and saving the output to correct.h. The included correct.h files are from running on an atmega8 chip.