Trouble with voltage/current regulator [SOLVED]

Go To Last Post
8 posts / 0 new
Author
Message
#1
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I constructed (what should be) an auto-selecting voltage OR current limiter using a two comparators and a fet driver that has an internal AND gate. The fet drives the field of an automotive alternator. Two potentiometers are used to set the voltage at the non-inverting inputs, and then the inverting inputs are connected to the alternator output and a current shunt. Voltage dividers are used to get the proper voltage levels.

I have attached a schematic I drew in LTSpice. I did not show the power/ground for the chips or the decoupling caps that are across each chip. As it sets on the bench, running on battery, it has extreme internal noise and instability. I assume that the output switching is causing the sensed input state to switch as well. Adding some positive feedback hysteresis to (one of) the comparator/s helped, but did not fix the noise. The noise is only going to get worse when the engine is running and the alternator/s are outputing DC with 400+ Hz ripple plus whatever HF junk couples onto our signal lines from the ignition. Furthermore, the amp shunt is only dropping 1 mV per amp. At 400-500 amps that is a lot of power lost, and not much signal. Never mind the 60Hz sine wave that's ever present on everything.

The fet driver does have an AND gate, and two hysteresis' but I am treating the the input and enable as if they are equivalent; perhaps they are not. (See pp. 2) My circuit seems to work better (but still not correctly) if I have ONLY the voltage OR current limiter connected to the INPUT, and leave the enable pulled up.

I've been fighting with this for several days now. I do not consider myself as giving up, but rather that I have been beaten. Maybe I just want to cut my losses and find plan B. I have other ideas of how I might go about eliminating the dual comparator; maybe something involving several BJT's that I have not quite yet figured out in my mind. Maybe I'm missing something important with what I have.

Thank you for your time and consideration.

Attachment(s): 

Last Edited: Fri. Dec 24, 2010 - 07:05 PM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

You may have input voltage limit problems with the comparator that senses current. Its hard to tell since you don't show any supply voltages.

Also, you are trying to control a linear system (the alternator field) digitally. You would be far better off with a PWM system, I think, rather than an "bang-bang" (hard on, or hard off) system. What you have will be inherently noisy and unstable.

Jim

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Thank you for your reply.

I have attached another schematic that is more indicative of what I have (power/ground, decoupling caps). Though, currently, it is just running a couple-watt incandescent light bulb. The alternator field is not even in the circuit, nor is the engine running.

What you say about using PWM, and please forgive my simplistic idea, but would that involve a 555 timer, and maybe some RC filters on whatever the inputs are to smooth the signals?

I'm thinking here; have the volt and amp set pots function as pullups on the dutycycle control of the 555, and the sensed voltage and current act as pulldowns thru a bjts (to invert) on the dutycycle control? Maybe parallel the inputs to the 555 with resistors like is done with a summing op amp. I have also attached a schem of this. Resistor selection would be of vital importance. I know the 555 doesn't have a dutycycle control. This is just a rough gist.

This rough idea of mine fails because one could set either pot at zero, and the other would still be able to pull the dutycycle line up and cause output. I clearly did not grasp what you suggested :(

Attachment(s): 

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Your shem3 is probably the worst of all worlds. The transistors will simply not function as you would like and will give huge problems due to changes in base voltage with temperature and beta with temperature.

The preferred way, these day, is a micro (does not have to be AVR, could be PIC, or MSP430, or other) with analog digital converter to read the two several inputs. You use these readings to determine the appropriate duty cycle of a PWM output. The PWM drives the FET. With a few additional details, you are basically done.

Jim

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Have in mind that LM 393 is a comparator and its output
is open collector.That means it needs a pull-up resistor.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I had wanted to use the AVR from the start, but the design was feature creeping on me and I thought I could get it going quickly with the comparator. I sure saved myself a lot of time with that one. :roll:

...guess I will break out the programmer.
But hey, code reuse is awesome :)

Thank you for your input.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

...and that's another mistake on the schematic. I realized the open collector issue just in the nick of time to avert tragedy.

I did however fail to depict the pullups on the schematic. Thank you for pointing that out.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I gave it one more try using some ideas I had, and made it work. Let me tell you; it's a beautiful thing :)

The three changes are;
1) The outputs of the 393 are only open collectors; they won't fight. I just paralleled them into the INPUT of the fet driver. Previously I had one 393 output to the INPUT of the fet driver and the other output to the ENABLE.

2) I added a pullup to ENABLE B and a pulldown to INPUT B. This is just to make sure it stays in *A* state and does not have spurious transitions adding noise; it is probably not necessary. I left the pullup on the ENABLE that I am longer using. The ENABLEs have internal pullups, but I just wanted to be sure.

3) I added an RC filter between the outputs of the 393 and the input of the fet driver.

The fet also has a gate-source pulldown on it; I don't remember the exact value, but it's not that important. I failed to depict this on previous schematics. The fet I'm using is the FQP50N06L, not the 2N7002. (I failed to edit the schematic)

I had installed two pots between the fet driver output and the 393 inputs (along with a pair of fixed resistors to limit current if the pot was at zero) This was to function as hysteresis to slow system transitions. It was not necessary, so I removed it. This is not depicted on the schematic.

With the engine running, the voltage that the chips are getting is quite clean. I am a bit surprised, those decoupling caps must be doing their job. The voltage regulation is quite aggressive when seeking a higher voltage/power output, but I have not noticed any oscillation in voltage control. It also has excellent voltage regulation under no load conditions. It does overshoot for just a moment when a smallish (100 amp) load is removed, but this is not an issue for me. I have not looked at overshoot under heavy loads. I think some sort of crowbar circuit would be needed to prevent this; my 40V/40A bench supply has one such circuit.

All in all, I am very, very happy with the outcome of my labors. :) I am especially happy with how simple the circuit is, particularly considering what it accomplishes (automatically limiting voltage OR current). I would also hope that others might benefit from my efforts.

Thank you to all who looked at, considered, and responded to my thread.

Take care,
-zphere

Attachment(s):