AVR Freaks

The Bus voltage of the LC network is 540VDC. (3 phase 400VAc rectified). 

In the simulation , If I choose an overdimensioned C like 100uF the voltage on the capacitor does not exceed 15Vpeaktppeak. The huge part of the voltage stays on the inductor.

But some design paper suggest to use high voltage rated capacitors even if the capacitor voltage does not exceed 15Vpeaktopeak in steady state.

I do not trust the simulation software in dynamic state. I can avoid huge changes of the PWM duty cycle in the embedded software code. But even then there may be some situations like ex. where i should handle shorted secondary of the transformer and in this case there may be a huge fluctiuation in the volt-second balance of the transformer. This may increase the voltage on the series capacitor. But I am not sure of that.

The critical question is that in an LC network if we choose overdimensioned C (ex 100uF) and a small enough L, can we *always* guarantee that in all working condition (both steady state and dynamic ) the voltage on C stays below a certain limit (ex: 20V) 

I assume the obligatory condition is that we are working far away from the resonant frequecy of the LC network. But even then I am not sure if some complication can occur at startup and shutdown of the network.

My working frequency ist 50khz.  The resonance frequency of LC circuit ist at 3.5khz.

I fear if at startup or shutdown some portion of the morphing frequency tends to get some amplification nearing the resonance frequency and the capacitor is damaged because of high voltage. 

The first implementation will be up to 15A @50khz.

If I stay far from resonance frequency of 3.5khz, it seems that the cap voltage will never go beyond 20V.

I constructed a capacitor bank consisting of 50V,10uF MLCCs because of cost optimisation.

The group1 of capacitor bank is made of  4 series connected 50V 10uF (MLCC ,case 1206), each balanced with 47k paralel resistor network.

Group1 resulting cap is 200V 2.5uF

x10 group1 connected parallel so the resulting cap is 200V, 25uF.

The resulting PCB with heavy copper (105um) ist poured into resin epoxy.

Does anyone have experience with balancing the series connected capacitors through paralel resistor networks when working under high frequency?

They seem to be excellent capacitors. But IMHO for 25uF @1000V they will be much more expensive than the alternative film capacitors.

For this kind of severe current range jumping from -15A to 15A, I also can not predict if the ceramic body mechanically withstand the osscilations. A series connected pulse capacitor carrying the whole line current with a ripple current of +/-15A is a very different story from a smootening or snubber capacitor. 

They are really expensive:

700VDC 1uF cap cost around 13.5 Euro/each for a quntity of 1000. My 25uF cap bank should cost around 337.5 Euro. The film capacitor bank costs around 7.5 Euro, but is not the 1:1 alternative. 1000Vdc film cap has only 20V Voltage rating at 50khz. 

http://eu.mouser.com/ProductDetail/TDK/B58035U7105M062?qs=sGAEpiMZZMtGtrSL1omHbHPJTSb0%2fcOqdqjlg8RO1I8%3d

Thanks for the links. I have investigated the above links a while ago. The problem is :

If you increase C the voltage stress on c decreases, but you will need to increase the resonant inductor so that the minimum current where the soft switching begins remains low. This is not so straighforward. They don't explain in the paper (chineese) how they overcome the problem that the minimum current for the soft switching becomes too high. It would be better that they give the Lr and Cb values so that I could simulate it to see if the claims are justified.

If you decrease the value of C, you have more room for soft switching because the inductor has enough energy to balance the enegry stored in Capacitor. But then you face 2 main problems: 1-The voltage rating of the capacitor will be very high and it will be very expensive. 2-This will also limit the power transfer and duty cycle.

All these can be overcomed by nearing to resonance frequency and controling the power flow through a kind of frequency modulation. It is the famous LLC converter. But it has also drawbacks. 

Short: Nothing is perfect.  

Yes absolutely true,

Q=C.V

And unfortunatelly, it is not a resisitive element. It means any fluctuations in V means the existence of current. they are connected.

dQ/dt = C. dV/dt

And if we are talking abaout frequency, it means that dV/dt must be huge so the term dQ/dt. dQ/dt is nothing others than the  I, current.

Passing huge amounts of current through huge dV/dt means extreme power dissipation:

W= 1/2 * C* V^2.  This is the stored energy, but the dissipation is also very high because of very high ripple currents.

Thanks for your input.

I investigate the distrubutors inventory (mainly mouser). 

My main problem for MLCC ceramics is that the ESR is not well defined.

For example for the film cap 1uF, 1000VDC the internal ESR is given as 9mOhm. If I=15A. I can calculate that the power dissipation is 15x15x0.009= 2watts. The case of film caps are huge (27.5mmx10mmx15mm). So I can be sure that 2W is compatible for the dimension of the case.

But for the ceramics there is a problem with the ESR. Ok, we know that it is very low, but as far as I noticed in the datasheets it is also heavyly frequency dependant.  I can not calculate it precisely. Is it 10mOhm or 1mOhm?. Not clear from the logaritmic graphs that is available in the datasheets. The case of the ceramics are also very small. So any misscalculation of the effective ESR will destroy the chip . think how small is the 1206 case. It can definitely not dissipate 2W. There is also the risk of a mechanical crack.

I investigate further.