Tiny26 & SPI

Go To Last Post
8 posts / 0 new
Author
Message
#1
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Hi,

I've been having problems generating a clock for the 3 wire-mode USI (SPI). The Timer0 is initialized and working. I would like to use Timer/Counter0 overflow option for generating the SCK for SPI. I've set the USICR=0x14 and the clock should then be generated if the Timer/Counter0 is running(?). Both TIMSK and TIFR have been set to 0x00.

Any ideas why I have no SCK?

11011110101011011100000011011110

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

If TIMSK=0 the timer won't generate and interrupt.
P. 36 in the data sheet:

Tobias

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I've got the SCK to work by using an interrupt routine and then toggle the pin. But I would R E A L L Y like to know how the SCK with USI is supposed to work.... I think I've only done a work-around, because I think the SCK i supposed to be automaticly set when I config the USICR? Or am I wrong? Anyone?

11011110101011011100000011011110

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I gave a quick read to the datasheet sections on SPI, and while not as clean as a hardware SPI, it looks like a good explanation.

Are you saying that using the code fragments from the datasheet do not work? In what respects do they give different results? I did see one mention of correct pin direction. Is DDRB set properly?

Lee

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Isn't Timer1 the one that's connected to USI (PB2) ?

admin's test signature
 

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Sorry for my confusion.... I located a fairly clear (and disappointing) statement in the data sheet. In Table 30 (page 66) it says "When operating as master, clock pulses are software generated by toggling the PORTB2 bit while DDRB2 is set to
output.....". The code at the bottom of page 69 shows software generation of the clock, not either TIMER0 or TIMER1.

This seems to contradict Table 31 which gives settings for using TIMER0 overflow as USI clock. Another contradiction is Figure 35, which clearly shows TIMER1 connected to PB2. Table 44 shows OC1B (Timer1 PWM B) as an alternate signal that PB2 can output.

BTW, I noticed that this data sheet was updated 9/02... the timer USI sections weren't changed.

admin's test signature
 

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Lee:
I haven't used code from the datasheet as I prefer to write in C. DDRB should be set correctly as it is set to 0x05.

Mike:
No, it's Timer/Counter0 (Table 31, page 67).

I'm currently working on getting it to comunicate with a stand alone CAN-controller (MCP2510). I'll inform you when it works.

11011110101011011100000011011110

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

puhh...

I'm only human...

After several weeks of frustration it all works now. I've received a couple of mails concerning the SPI interface, but I can tell you to my relief: it works fine. My current driver uses the USIDR-register and is duplex and operates on fck/2. I've configured it to work with a MCP2510.

I must say, it isn't easy reading a datasheet when you confuse 0x0E with 0xE0...

The chip is ok, sorry I can't say the same for my head though :-)

admin's test signature