Timer0 Overflow interrupt Never Happens (newbie)

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I've set LEDs, built an up/down counter, and played with the gnu toolset. Now I'm trying to move on to interrupts, and I'm having some trouble. I wrote a simple C program (which is included below for reference) which is a timer0-based up counter. The LED setup works (I can set the values manually and they display correctly), but the intterupt vector is never called (or at very least, none of the effects are seen). I'm using the latest GNU toolchain and an STK500, and I've checked the internal OSC setting on the STK500. It seems to be set appropriately. I've changed it up and down, but to know effect.

I am most likely missing some initialization step (like the Gen Int Enable on the PICs maybe?), but the thing that bothers me is that I downloaded sample code to help me debug my problem, and the sample code's interrupt routine is not firing either. The sample code was from a tutorial on using interrupts on the AVR from http://members.shaw.ca/climber/a.... I've looked over the Academy's sample code, but most of it is assembly, and my code looks consistent with Design Note #024.

Any help the community can provide would be appreciated. Thanks.

-Bob

--- Simple C Code Starts Here ---
#include
#include
#include
#include

#include
#include

uint8_t counter;

// timer0 compare match interrupt handler
SIGNAL(SIG_OUTPUT_COMPARE0)
{
counter++;
PORTD = ~counter;
}

int main(void)
{
counter = 0x01;

// Set up LED output
DDRD = 0xff;
PORTD = 0xff;

// Init timer zero
TCCR0 = BV(WGM01) | BV(CS02) | BV(CS00); // CTC Mode, 1024 prescalar
TIMSK = BV(TOIE0); // Turn on overflow interrupt
SFIOR |= BV(PSR10); // Strobe the timer-reset register

// Interrupts are OK now...
sei();

while(1) {
asm volatile("nop" ::);
//PORTD = ~counter;
}

return 0;
}
--- Simple C Code Ends Here ---

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You have defined one interrupt, while enabling another.

You have defined the Output compare interrupt and have enabled the overflow interrupt.

Writing code is like having sex.... make one little mistake, and you're supporting it for life.

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There are several types of timer/counter interrupts. In particular in your case, it appears that you are telling the AVR to give you an interrupt on a timer overflow (TIMSK = BV(TOIE0); // Turn on overflow interrupt but your ISR will catch a compare match (SIGNAL(SIG_OUTPUT_COMPARE0) )

Which AVR? I'm not familiar with your tools, but you might want something like TIMSK = BV(OCIE0)

[Also, you may want to edit your posting and try out the "Code" formatting--it does a better job of preserving spacing, and the light background is easier on geezer-eyes.]

Lee

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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Oh, BTW, AVRStudio simulator works pretty well for programs of the type that you posted and you should be able to tell step-by-step what is happening.

Where the sim will not be as useful is with the microcontroller subsystems such as PWM, A/D, UART, etc.

Lee

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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First, thanks to you both for replying. As it turned out, using SIG_OUTPUT_COMPARE was a vestige from one of the things I tried, I had forgotten to reset it to its original (limber's code was an output-compare example, so I temporarily tried implementing that instead of an overflow counter). After toying with prescalar values some more (pushing them up to 1024), I finally saw a delay. As it turns out, I had neglected to realize that the ATMega16 I was using ships with its fuses set for the internal osc. This meant that while I was expected a 1KHz clock (I had the prescalar set at 256 earlier), I was actually getting 1,000 times that. This meant everything looked instantaneous. I set the fuse lowbyte to 0xef, and the thing worked right off. Should've thought of that earlier.

Again, thanks for the help, guys. I'll continue my quest through the interrupt scheme. Back to hackin'.

-Bob

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volatile uint8_t counter;