TCC0 CTC mode??

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I'm trying to replicate the "simple" CTC mode for timer0, but NOTHING is simple with the Xmega. :evil:

The timer is running, the IVEC_TCC0_CCA_vect ISR fires but the overall time is out by about 256 times!! (Supposed to be 4ms)

The clock is running at 4MHz but I don't understand if this is also the peripheral clock.

TCC0_CTRLA is at the moment at DIV1 (was 64)

TCC0_CTRLB is set for FREQ which supposedly has CCA as top.

TCC0_CCA is set at 250

the old formula was 250ns*64*250=4ms so I guess that the timer clock is not the 4MHz.

I have 2 LEDs toggling in the ISR at 100ms and 1s but I can see that the 1s led is flashing at 4s (stopwatch timed) and the 100ms led looks more like a 400ms flash.

Other timers are also out by a factor of 4 (x64 or 256x if I set the prescaler at 64 which was)

Can anyone shed any light on this please? :)

John Samperi

Ampertronics Pty. Ltd.

www.ampertronics.com.au

* Electronic Design * Custom Products * Contract Assembly

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arghhhh by setting the mode to BYTE mode (8 bits?) it all works! I guess this brings the timer back to the normal 8 bit timer0 mode of the AVR?

I don't see how it should make any difference as TCC0_CCA is still set at 250 either way. :roll:

Spend most of the afternoon on this.

John Samperi

Ampertronics Pty. Ltd.

www.ampertronics.com.au

* Electronic Design * Custom Products * Contract Assembly

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For working XMEGA timer as AVR CTC mode, you can change Period register in normal mode (TCC0_PER). And for the rest of problem, I would be glad to help if you put your sample code (setting clock to 4MHz, ...).

Ozhan KD
Knowledge is POWER

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Well it's all working ok now in BYTE mode, but enjoy.. :-). (edit see fixed code below)

I guess I don't really need to set TCC0_CCAH any more

;Set clock to 4 MHz
	ldi		temp, 8					; PLL mult. factor ( 2MHz x8 ) and set clock source to PLL
	STORE	OSC_PLLCTRL, temp
	ldi		temp,(1<<OSC_PLLEN_bp)	; Enable PLL
	STORE	OSC_CTRL, temp
PLL_not_ready:
	SKBS	OSC_STATUS, OSC_PLLRDY_bp, temp2	; Is PLL clock ready to go?
	rjmp	PLL_not_ready
	ldi		temp,CCP_IOREG_gc		; Unlock sequence to access CLK_CTRL
	STORE	CPU_CCP, temp
	ldi		temp, CPU_CCP_offset	; Select PLL as system clock 
	STORE	CLK_CTRL, temp

	ldi		temp,CCP_IOREG_gc		; Unlock sequence to access CLK_CTRL
	STORE	CPU_CCP, temp
	ldi		temp, CLK_Divide_by_4
	STORE	CLK_PSCTRL, temp
.
.
.
.
;Timer0 compare tick every 4ms from 4MHz, used for 100ms and 1s soft timers
	ldi		temp,T_CLK_DIV64	 		; clk/64
	STORE	TCC0_CTRLA,temp

	ldi		temp, (1<<FREQ)				; CTC mode	
	STORE	TCC0_CTRLB,temp

	ldi		temp, low(250)				; Compare set for 4ms (250ns*64*250=4ms)
	ldi		temp1, high(250)

	STORE	TCC0_CCAL,temp
	STORE	TCC0_CCAH,temp1

	ldi		temp, (1<<BYTEMODE)
	STORE	TCC0_CTRLE,temp

	ldi		temp, (1<<CCAINTLVL_LO)		; Low level priority
	STORE	TCC0_INTCTRLB, temp

	ldi		temp,25						; 25*4ms=100ms
	mov		time_scaler,temp			; Initialise scaler
	ldi		temp,10						; 10*100ms
	mov		one_second_timer,temp		; Initialise one second scaler

John Samperi

Ampertronics Pty. Ltd.

www.ampertronics.com.au

* Electronic Design * Custom Products * Contract Assembly

Last Edited: Mon. Dec 10, 2012 - 11:41 PM
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If I assume STORE and SKBS as different names (macros) for STS and SBRS, CLK_Divide_by_4=12, T_CLK_DIV64=5, FREQ=0, BYTEMODE=0 , CCAINTLVL_LO=0, the code seems to be correct (except 250 for CCA value. 250 must be 249 according to one additional clock for 249-->0).

Ozhan KD
Knowledge is POWER

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Quote:
If I assume STORE and SKBS as different names (macros) for STS and SBRS
They are official Atmel assembler macros from AVR001, when I'm working in assembler I have pretty much stopped using in/out, lds/sts and other instructions which may not work with some chips.

As the code is written it is more than 90% portable to the Xmega from the Mega chips.

Quote:
CLK_Divide_by_4=12, T_CLK_DIV64=5, BYTEMODE=0
Yep. :oops: The other 2 are 1 bit off, so I'm really working in split mode rather than byte mode and the "freq" is putting the chip in some reserved mode.
I'll need to fix those.

I'll also fix the 250, I vaguely remember something about a clock cycle but I thought it had something to do with 32bit mode.

John Samperi

Ampertronics Pty. Ltd.

www.ampertronics.com.au

* Electronic Design * Custom Products * Contract Assembly

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I have fixed the code using the defintions in the .inc files, I think I'm starting to get my head around it. :roll:

It now works both in byte mode and normal 16 bit mode, I may have messed up one of my definitions.

;Set clock to 4 MHz
	ldi		temp, 8					; PLL mult. factor ( 2MHz x8 ) and set clock source to PLL
	STORE	OSC_PLLCTRL, temp
	ldi		temp,(1<<OSC_PLLEN_bp)	; Enable PLL
	STORE	OSC_CTRL, temp
PLL_not_ready:
	SKBS	OSC_STATUS, OSC_PLLRDY_bp, temp2	; Is PLL clock ready to go?
	rjmp	PLL_not_ready
	ldi		temp,CCP_IOREG_gc		; Unlock sequence to access CLK_CTRL
	STORE	CPU_CCP, temp
	ldi		temp, CPU_CCP_offset	; Select PLL as system clock 
	STORE	CLK_CTRL, temp

	ldi		temp,CCP_IOREG_gc		; Unlock sequence to access CLK_CTRL
	STORE	CPU_CCP, temp
	ldi		temp, (CLK_PSADIV_4_gc | CLK_PSBCDIV_1_1_gc)
	STORE	CLK_PSCTRL, temp
.
.
.
;Timer0 compare tick every 4ms from 4MHz, used for 100ms and 1s soft timers
	ldi		temp, TC_CLKSEL_DIV64_gc 	; clk/64
	STORE	TCC0_CTRLA,temp

	ldi		temp, TC_WGMODE_FRQ_gc		; CTC mode	
	STORE	TCC0_CTRLB,temp

	ldi		temp, low(249)				; (249 + 1) Compare set for 4ms (250ns*64*250=4ms)
	ldi		temp1, high(249)

	STORE	TCC0_CCAL,temp
	STORE	TCC0_CCAH,temp1

;	ldi		temp, (1<<TC0_BYTEM_bp)
;	STORE	TCC0_CTRLE,temp

	ldi		temp, (1<<TC0_CCAINTLVL0_bp) ; Low level priority
	STORE	TCC0_INTCTRLB, temp

	ldi		temp,25					; 25*4ms=100ms
	mov		time_scaler,temp		; Initialise scaler
	ldi		temp,10					; 10*100ms
	mov		one_second_timer,temp	; Initialise one second scaler

John Samperi

Ampertronics Pty. Ltd.

www.ampertronics.com.au

* Electronic Design * Custom Products * Contract Assembly