Taking Osccal to extremes

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I guess (with a 32.768k async on T2) a program could be written to sweep OSCCAL through all 256 steps from 0 to 255 and at each then profile the clock and store the speed to EEPROM to get a complete sweep of what F_CPU (and hence what UBRR) can be achieved at each step.

It's interesting he seems to have had one device that can do 5.3M..17.78M and another does 3.9M..13.9M - that's quite an unexpected variation between devices.