Dear all
In my spartan 3 (XC3S400) board i have a 50MHz clock that is connected to two clock pins (80 and 180). they are in different sides of the chip. i think by using this approach i can achive higher speed designs! now i want to know how to use this feature to define for ise that the two clocks are the same!
any ideas are welcome :idea:
Taking the advantage of two clock pins on fpga!
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huh? you don't need to use two clock pins with the same clock... it is not going to increase the speed of your design. The clock lines are fanned out within the chip with equal propagation across the chip. [within the chips ratings]
FPGA's quite often have several clock pins, each one belonging to a separate clock domain on the chip.
If you need to increase speed, you may be able to do so by having a phase delay delay on your clock, and applying that to two or more clock pins (90 degrees for 2 pins). This will give you multiple switching edges within the same period. However, you will still be limited by the gate propagation of the chip itself, so you need to ensure that your edges are far enough apart so that latching will occur on a valid state.
Two Clocks:
___ ___ ___
CLK0 __/ \___/ \___/ \___
___ ___ ___
CLK1 \___/ \___/ \___/ \_
Four Clocks:
___ ___ ___
CLK0 __/ \___/ \___/ \___
___ ___ ___
CLK1 ___/ \___/ \___/ \__
___ ___ ___
CLK2 \___/ \___/ \___/ \_
_ ___ ___ ___
CLK3 \___/ \___/ \___/ \
The speed of your design is limited by the propagation sum of the logic you are implementing, not by how far the cell is from the clock input pin.
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You can use the PLL, of course, to multiply the input clock.
This is sort of off topic from the main post, but does anyone have any recommendations for good FPGA (Xilinx Spartan 3 specifically) forums?
Thanks.
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Xilinx has their own forums, they are pretty good. I formed one specifically for the S3 Digilent/Xilinx kit:
leon_heller wrote:
You can use the PLL, of course, to multiply the input clock.
If the particular model has it... not all do. [haven't looked to see if the XC3S400 does or not]
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Of course they do! It's called a DCM and all S3 chips have four, except the XC3S50 which only has two.
Didn't realize all the Spartan3's had the DCM, could have sworn I came across some that didn't. I stand corrected.
Either way, you are speed limited by the grade of the chip, and the logic design. Routing the same clock to multiple clock pins is not going to improve anything.
Hi
this idea came to me from seeing a design of pci card from altera. almost any two clock pins were connected to the same input clock.maybe bye this way we can reduce the clock load and increase the speed of design!
Maybe these clocks are differential LVDS signals?
Last Edited: Sun. Dec 6, 2009 - 09:55 AM
Quote:
Maybe these clocks where differential LVDS signals?
I'm sure that they are ususal clock signals.
Bottom line is that it will not speed things up. Perhaps it is something with Altera, or the way they floor-planned their design. Either way, you are limited in speed by the grade of the part, and your logic design.
In any case your two clocks are separate nets, you cannot, nor do you want to, tie them directly together. You simply select one or the other in your logic blocks. Then when floor-planning you can place the blocks closest to the input clock, if you feel this is going to give you better performance.
Also note that using multiple pins does not decrease the load on the line, it increases it. The resistive component goes down, thus causing more current to be drawn. But the real killer is the capacitive component, and by connecting 2 pins to the same net, you have doubled the capacitive load, something which can be very detrimental in a high speed design.