Synchronization unit in timer2 ?

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I need to know more explanation about this synchronization unit  , because it might help in understanding the asynchronous operation of timer (that seems to me obscure ) ,any one could help please?

Note : the micro-controller is atmega32.

 

I am living to bring up new earth ,and not to eat and destroy earth.

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With synchronous digital logic you have one clock. From this you can hopefully ensure that all setup and hold times can be met over the full temperature, voltage and frequency. If you don’t know what setup and hold times are, then read up on flip/flops. If you violate these parameters, at best the flip/flop can assume the wrong state, at worst it can oscillate in a manner called ‘metastability’. Another keyword to Google.
If you have an asynchronous signal entering a synchronous system, you cannot guarantee the setup and hold times will be honoured. Thus a synchroniser circuit is used to lessen the possibility for metastability. This is made from a couple of flip/flops and some logic. The down side is that it delays the input signal by a couple of clocks. The term ‘clock domain’ is also usedto describe the situation. Timer2 with a 32kHz oscillator is one one clock domain, whereas the AVR core is on another. You need a synchroniser stage to cross clock domains.

You’ll also find there is a synchroniser stage on the input pins. This incurs a one clock delay.
I’ve given you plenty of keywords to Google.

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Kartman wrote:
You’ll also find there is a synchroniser stage on the input pins. This incurs a one clock delay.

As shown here in the data sheet about I/O ports:

The first FF grabs the data state and holds it steady for the second FF to hold for the I/O read request, the result of this, if you change the output of the PORT, it takes two clock changes for the INPUT to change to match the new OUTPUT value.

So if you want to read what your just wrote to a port, you need a NOP between the write port, read port...   i.e.  write port; nop; read port;

 

Jim

 

 

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