Suggestion for code execution from mmc

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Hi to all,

Program codes must be placed in flash due to AVR architecture. I have a suggestion for using mmc/SDC/SDHC or other storages for storing codes much greater in size than microcontroller flash capacity. The key solution is ICALL instruction. Different codes can be written in flash with a RET instruction after every code.A high level software can translate the original assembly code to address of each code in flash and this address is unique for every different instruction. Main program reads these addresses from mmc and loads Z register and then ICALL(EICALL) instruction will jump to instruction location and then returns by RET.For example (mov r16,r17) is written only once in flash. But can be executed several times.
Although some instructions can not be treated by this method. But very long codes can be stored and executed.

Ozhan KD
Knowledge is POWER

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Sounds like you just reinvented FORTH.

Stealing Proteus doesn't make you an engineer.

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I don't get it yet. You want to load a subroutine from the sd card into where? Ram or flash? You cant load it into flash more than 100,000 times or whatever. You cant execute it if its in ram, unless its the code for an interpreted language like forth or java or ?? so where the win with this new scheme?

Imagecraft compiler user

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This has only been discussed about 100 times. Put "p-code and Java" into your search and you'll find all the prior traffic.

Probably the closest anyone's got to a solution to this is NanoVm (mini Java for AVR):

http://www.harbaum.org/till/nano...

But also check out the CP/M system on AVR - that runs a Z80 emulator and can run Z80 opcodes out of SRAM, SD card or whatever.

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Thanks for your comments.

bobgardner wrote:
I don't get it yet. You want to load a subroutine from the sd card into where? Ram or flash? You cant load it into flash more than 100,000 times or whatever. You cant execute it if its in ram, unless its the code for an interpreted language like forth or java or ?? so where the win with this new scheme?

Suppose 1000000 lines of assembly program with 5000 different instructions and operands in this program. Most of similar instructions including load and store types can be saved once in flash followed by a RET. This 1000000 lines program can be converted to a very limited size of program in flash plus a large number of data in mmc.
The program reads the address of each instruction from mmc and loads Z register in a loop. Then ICALL jumps and executes the related instruction from a fixed table.
In this table each required instruction is present once. For example if there are 20000 times of (Mov r0,r16) in program, this can be reduced to one time by the following code in flash and 20000 times of addr0 in mmc.
For example:

Flash_table:
addr0:
mov r0,r16
ret
addr1:
mov r0,r17
ret
…

Data in mmc:
addr1
addr0
addrm
addrn
addr0
…

Ozhan KD
Knowledge is POWER

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I started on something like this a while back on a CPLD. it was going to be an AVR-like system that had 64K program memory, 64K SRAM, and 64 IO pins. It would have to lookup each instruction (AVR assembly-like), but at 100MHz, would give the program about 50MIPs speed.

The project evolved into a graphics type language, but has been on hold for about 2 years.

If you roll ahead, post your progress!

By avoiding flash read/write, it would be easy to make a 100MIPs generic AVR I think. Ubicom did it with PIC once!

Brad

I Like to Build Stuff : http://www.AtomicZombie.com

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This would, of course, be deathly slow. Your main loop would look something like this:

fetch_plus_1:
ADIW PC2:PC3, 1      ;2 cycles
fetch_opcode:
...
OUT SREG, status     ;1 cycle
ICALL                ;7 cycles (3 for ICALL, 4 for RET)
IN status, SREG      ;1 cycle
ADIW PC0:PC1, 1      ;2 cycle
BRCS fetch_plus_1    ;1:2 cycles
RJMP fetch_opcode    ;2 cycles

Which means at least a 14 cycle overhead for every instruction, and that doesn't even include fetching from the mmc. Plus any instruction that changes the PC (beyond the standard +1) would need several more instructions since they would need to adjust your virtual PC and restore SREG. And some instructions would also affect your virtual SP. So I would say at least 20x slower than from flash.

You would also sacrifice several registers. Of course the Z register (R30, R31) is out since you need it for the ICALL, plus 3 or 4 for the virtual PC, two for a virtual SP and one for saving SREG,

You also need special handling for interrupts, and JMPs and CALLs would not span the entire code range.

Regards,
Steve A.

The Board helps those that help themselves.

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Special thanks to Koshchi.
This method would be useful in non time critical applications.

Ozhan KD
Knowledge is POWER