Thanks to the chips Brian sent me, I have now analyzed the process of how to connect to the UPDI interface. This will eventually allow me to write my STK500v2 to UPDI interface, the objective is to turn a common arduino into a UPDI programmer.
But, to start at the beginning, I'm using as sources of information, the xtiny datasheets, of course, but also the pyupdi program done by Atmel people.
So, the first thing is to enable the UPDI peripheral. According to the datasheet, this should be done:
When the pull-up is detected, the debugger initiates the enable sequence by driving the line low for a minimum of 200ns and a maximum of 1us to ensure that the line is released from the debugger before the UPDI enable sequence is done.
The negative edge is detected by the UPDI, which requests the UPDI clock. The UPDI will continue to drive the line low until the clock is stable and ready for the UPDI to use. The duration of this will vary, depending on the status of the oscillator when the UPDI is enabled. A start-up time between 10us and 200us can be expected.
After this duration, the data line will be released by the UPDI, and pulled-high.
But when I looked at the pyupdi code, this initialization sequence was nowhere to be found, instead, a double-break sequence was seemingly used (see datasheet for details on what this is). I could be wrong, because my understanding of python is weak.
But anyway, I tested, and indeed the UPDI can be enabled in this alternative way, which greatly simplifies things, because this double-break sequence is also used to recover from errors. The datasheet says:
A double BREAK is guaranteed to reset the UPDI from any state.
So it seems, "any state" includes the disabled state, right after power on. And it's so much simpler than the "proper" enable sequence... This should be more clearly explained in the datasheet.
Ok, enough talk, I'll show some scope traces now. The yellow trace is the programmer side, blue is target (UPDI) side. Between them is a 4.7k resistor, and VCC is +5V for both.
First, a double break sequence:
This is just as recommended in the datasheet, a pulse of 24.6ms (that is 12 bits at lowest supported baud rate), followed by 1 stop bit, repeated twice.
Next trace is a close up on the first falling edge of the first double break sent immediately after powering up the XTiny, you can see that after less than 200ns (this time depends on input capacitance and resistor value), the UPDI reacts by setting the line as low output. Then, after less than 10us, it releases the line, so at the UPDI side, it drifts to a level set by the ratio of the 4.7k resistor and the UPDI pull up. At this moment, the UPDI is enabled.
Finally, on any subsequent double breaks, since the UPDI is already enabled, it doesn't respond by setting a low output state; instead it just stays as input:
Ok, that's it for now, next I will try to start talking to the UPDI.