I'm using the SSC and PDCA in an AT32UC3A3256 to implement two-way I2S. For now I'm focusing on the TX side where both SCLK and LRCK are generated by the MCU. I keep reading rumors of SSC silicon bugs. Have you had any success with reliably using the SSC for I2S signas?
The code I'm working on is open source. I'd like to share any workarounds for SSC-I2S.
In my code there is non-zero probability that the left and right channels are swapped, i.e. polarity inversion on LRCK. I'm able to reduce the probabiltiy by timing calls to pdca_enable(), pdca_init_channel() and pdca_enable_interrupt_reload_counter_zero() relative to LRCK edges. But I'm not able to reduce the probablility of channel swap to zero. Strangely, the probability of inversion seems higher on the 2nd reset after DFU. I can try to sqeeze the inversion issue out of my code, but when I change completely unrelated code it comes right back in.
There is a report of a race condition in ssc_pdc_start() at the bottom of this page: http://www.ultimaserial.com/avr_lwip_tips4.html
In the picture you see how LRCK is strange for the first period. I set PIN_PX18 just before I call ssc_i2s_init(). Is this full period of LRCK beign 1 to be expected? MCLK is provided externally, and SCLK is correctly generated by the MCU.
Any input appreciated!