SRAM with one R/W pin instead of a R and W pin

Go To Last Post
4 posts / 0 new
Author
Message
#1
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Hello all,

I am working on a project that involves hooking up SRAM to the AVR. The SRAM that has been chosen does not have separate read and write pins but only one read/write pin. True to my habit of trying it out myself first and than asking questions I have come up with a solution. I would just like to know if this solution would work or not. I’m sure some here have had some experience hooking up SRAM that does not have separate read write pins so I would just like to know if this is what you used (or not used but will work anyway). I am making the PCB next week without any breadboarding or testing so I would like to avoid potential problems the best I can.

I do not know if it is a necessary bit of information but I am using the ATmega162 and the SRAM is the CY7C007A which is a dual ported SRAM (that is why all the pins have the 'L' suffix which stands for the left side of the SRAM).

Thanks for any help,

Will

Attachment(s): 

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I've done a bit of SRAM interfacing and your approach looks like it'll work. Hopefully you've drawn timing diagrams which account for gate delays. Important! Not all 4081's are alike. I assume you're using one which is faster than about 10 nS.

What do you plan to do when you get a 'busy' ? :twisted:

Suggestion: Hook busy to an edge-triggered interrupt. If busy occurs during a write operation, then the write may have failed and should be repeated.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

The device labeled 4081 is actually an 11008 with a typical propagation delay of 6.3nS (max 10.2nS). I think I should be okay. The propagation delay actually seems to work to my advantage and eliminate any problems by making CE the last signal to change state. See page 11 of the CY7C007A if you’re interested and take note of note 32.

As far as my understanding goes the BUSY is used to indicate that both the left and right sides are trying to access the same address. So far I don’t need it because in the way everything should work there should never be a case where this occurs.

Thanks for your help,

Will

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Hi,

It looks to me like it will work. A quick other note is I think the ALE line could be used as well for the CE line, BUT you'd have to be careful as the ALE line will also pulse for internal SRAM access. However the WR pin wouldn't go active, which would mean it would just force a read of the RAM at that location, which may not be acceptable in your case (with dual-port and all).

Regards,

-Colin